Abstract: At least one processor may organize a plurality of primitives in a hierarchical data structure. The at least one processor may rasterize a plurality of bounding volumes associated with non-root nodes of the hierarchical data structure to an off-screen render target. The at least one processor may determine a bounding volume that is intersected by a ray out of the plurality of bounding volumes. The at least one processor may determine a non-root node of the hierarchical data structure that is associated with the bounding volume as a start node in the hierarchical data structure to start traversal of the hierarchical data structure. The at least one processor may traverse the hierarchical data structure starting from the start node to determine the primitive that is intersected by the ray.

Abstract: Techniques are described for stochastic rasterization. A graphics processing unit (GPU) may discard samples of bounding polygons that together indicate movement of one or more primitives before a pixel shader process the samples. The GPU may leverage a stencil buffer and stencil test for discarding of such samples.

Abstract: Systems and methods for a tessellation are described. The tessellation unit is configured to determine a number of points that reside along a first edge of a first ring within a domain, determine a first set of coordinates for a first portion of the points that reside along the first edge of the first ring within the domain, and determine a second set of coordinates for a second portion of the points that reside along the first edge of the first ring within the domain based on the first set of coordinates for the first portion. The tessellation unit is also configured to stitch points that reside along the first edge of the first ring with points that reside along a second edge of a second ring to divide the domain into a plurality of primitives that are mapped to a patch.

Abstract: Systems and methods for a tessellation are described. For tessellation, a tessellation unit may divide a domain into a plurality of portions, where at least one portion is a contiguous portion. The tessellation unit may output domain coordinates of primitives along diagonal strips within the contiguous portion to increase the likelihood that patch coordinates that correspond to the domain coordinates are stored in a reuse buffer.

Abstract: Disclosed herein is a vertex core. The vertex core includes a reset scanner configured to remove reset indices and partial primitives in an input stream and resolve draw calls into sub-draw calls at reset index boundaries; and provide the resolved sub-draw calls to a plurality of downstream vertex grouper tessellators.

Abstract: This disclosure describes a method for performing conservative rasterization in a processor comprising determining vertices of a primitive, defining edges of the primitive by determining a set of edge equations based on the determined vertices, wherein the edge equations are based on an edge shifting parameter plus an offset, determining pixels that touch the edges of the primitive using the determined edge equations, and rasterizing the primitive using the determined pixels.

Abstract: A graphics processing unit (GPU) may allocate a shared data channel in on-chip graphics memory of the GPU that is shared by at least two stages of a graphics processing pipeline. Shader units in the GPU may execute the at least two stages of the graphics processing pipeline. The GPU may store, in the shared data channel in on-chip graphics memory, data produced by each of the at least two stages of the graphics processing pipeline executing on the shader units.

Abstract: Techniques described in the disclosure are generally related to generating points of a domain. A tessellation unit may determine outer ring point coordinates for a point of an outer ring of the domain, and inner ring point coordinates for a point of an inner ring of the domain. The inner ring is inner to the outer ring within the domain. The tessellation unit may enqueue the inner ring point coordinates at a location of a queue, read the inner ring point coordinates from the queue, and read the outer ring point coordinates from the queue when the outer ring is not an outermost ring, where the outer ring point coordinates were previously enqueued in the queue when the outer ring was a previous inner ring. The tessellation unit may connect the inner ring coordinates and the outer ring coordinates each of which being read from the queue.

Abstract: Techniques described in the disclosure are generally related to determining the manner in which to connect points that reside along an outer ring edge and an inner ring edge for purposes of tessellation. For example, a two-dimensional (2D) stitching table may define the manner in which points along the edges should be connected together to form a plurality of primitives. The techniques may index the 2D stitching table to retrieve entry values that define the manner in which the points along the edges should be connected together.

Abstract: A graphics processing unit (GPU) comprises a memory, and at least one processor configured to: receive a primitive type buffer comprising a plurality of primitive type entries, wherein each of a plurality of vertices of a vertex buffer of the GPU are associated with one or more of the plurality of primitive type entries, determine primitives based on the plurality of vertices and the associated one or more primitive type entries, and rendering, by the GPU, the primitives based on the plurality of vertices and the associated one or more primitive type entries of the primitive type buffer.

Abstract: A distributed computing system includes a primary device and one or more backend devices. The primary device provides a management interface for the distributed computing system. A plurality of applications may be installed on the backend devices for execution. The primary device generates registration data that associates the applications with management interface commands or configuration parameters in response to messages received from the applications. Subsequently, when the primary device receives a particular command at the management interface, the primary device identifies, based on the registration data, a particular application from among the plurality of applications. In response to identifying the application, the primary device may send to the application an outgoing message.

Abstract: In an example rendering graphics data includes determining a stencil parameter that indicates a sampling rate for determining a coverage value for each antialiased pixel of a path of an image, determining, separately from the stencil parameter, a render target parameter that indicates a memory allocation for each antialiased pixel of the path, and rendering the path using the stencil parameter and the render target parameter.

Abstract: In an example, rendering graphics data includes determining, with a graphics processing unit (GPU), a texture offset for a current segment of a plurality of ordered segments of a dashed line, where the texture offset for the current segment of the plurality of ordered segments is based on an accumulation of lengths of segments that precede the current segment in the order, and pixel shading the current segment including applying the texture offset to determine a location of the current segment.

Abstract: A system, method and a computer program product are provided for distributing prim groups for parallel processing in a single clock cycle. A work distributor divides a draw call for primitive processing into a plurality of prim groups according to a prim group size. The work distributor then distributes the plurality of prim groups to a plurality of shader engines for parallel processing of the plurality of prim groups during a clock cycle. The size of a prim group and a number of prim groups are scaled to the plurality of shader engines.

Abstract: Disclosed herein methods, apparatuses, and systems for performing graphics processing. In this regard, a processing unit includes a tessellation module and a connectivity module. The tessellation module is configured to sequentially tessellate portions of a geometric shape to provide a series of tessellation points for the geometric shape. The connectivity module is configured to connect one or more groups of the tessellation points into one or more primitives in an order in which the series of tessellation points is provided.

Abstract: Methods, systems, and computer readable media embodiments are disclosed for generating primitives in a grid. Embodiments include generating a set of vertices in a section of the grid, selecting one or more vertices in the set of vertices in an order based on a proximity of the vertices to a boundary edge of the grid, and generating primitives based on the order of the selected vertices.

Abstract: A method, system, and computer program product are disclosed for providing tessellated primitive data to a geometry shader. The method comprises computing a set of tessellated vertices and a computed set of connectivity data based on an original set of vertices and an original set of connectivity data, generating computed vertex data based on the original set of vertices and the set of tessellated vertices, receiving the computed set of connectivity data, requesting a subset of the computed vertex data based on the computed set of connectivity data, and processing primitives defined by the subset of the computed vertex data. The system and computer program product are further disclosed for accomplishing a similar result as the aforementioned method.

Abstract: Systems and methods for a tessellation are described. For tessellation, a tessellation unit may divide a domain into a plurality of portions, where at least one portion is a contiguous portion. The tessellation unit may output domain coordinates of primitives along diagonal strips within the contiguous portion to increase the likelihood that patch coordinates that correspond to the domain coordinates are stored in a reuse buffer.

Abstract: A graphics processing unit (GPU) includes an indexed streamout buffer. The indexed streamout buffer is configured to: receive vertex data of a primitive, and determine if any entries in a reuse table of the indexed streamout buffer reference the vertex data. Responsive to determining that an entry of in the reuse table references the vertex data, the buffer is further configured to: generate an index that references the vertex data, store the index in the buffer, and store a reference to the index in the reuse table. Responsive to determining that an entry does not reference the vertex data, the indexed streamout buffer is configured to: store the vertex data in the buffer, generate an index that references the vertex data, store the index in the buffer, and store a reference to the index in the reuse table.

Abstract: Systems and methods for a tessellation are described. These systems and methods may divide the domain into a plurality of portions, including a first portion. The systems and methods may also determine coordinates for vertices for a first set of shapes that reside within the first portion, wherein each shape of the first set of shapes includes at least one vertex on a first edge of the first portion. After determining coordinates for the vertices for the first set of shapes, the systems and methods may determine coordinates for vertices for a second set of shapes that reside within the first portion. Each shape of the second set of shapes shares at least one vertex with at least one shape of the first set of shapes and none of the shapes of the second set of shapes includes a vertex on the first edge of the first portion.