Abstract: A system and method are presented by which data on a graphics processing unit (GPU) can be output to one or more buffers with independent output frequencies. In one embodiment, a GPU includes a shader processor configured to respectively emit a plurality of data sets into a plurality of streams in parallel. Each data is emitted into at least a portion of its respective stream. Also included is a first number of counters configured to respectively track the emitted data sets.

Abstract: Disclosed herein methods, apparatuses, and systems for performing graphics processing. In this regard, a processing unit includes a tessellation module and a connectivity module. The tessellation module is configured to sequentially tessellate portions of a geometric shape to provide a series of tessellation points for the geometric shape. The connectivity module is configured to connect one or more groups of the tessellation points into one or more primitives in an order in which the series of tessellation points is provided.

Abstract: A hardware tessellation circuit serves as a unified hardware parametric coordinate generator for providing parametric coordinates for tessellation. The tessellation circuit includes control logic that receives tessellation instruction information, such as an instruction indicating which type of multiple tessellation operations to perform, on an incoming primitive wherein the different types of tessellation include discrete tessellation, continuous tessellation and adaptive tessellation. The tessellation circuit also includes shared tessellation logic that is controlled by the control logic, and includes a plurality of shared logic units, such as arithmetic logic units, that are controllable by the control logic based on the type of tessellation detected to be used for the incoming primitive. The shared tessellation logic is controlled to reuse at least some of the logic units for two different tessellation operations defined by the tessellation type information.

Abstract: A hardware tessellation circuit serves as a unified hardware parametric coordinate generator for providing parametric coordinates for tessellation. The tessellation circuit includes control logic that receives tessellation instruction information, such as an instruction indicating which type of multiple tessellation operations to perform, on an incoming primitive wherein the different types of tessellation include discrete tessellation, continuous tessellation and adaptive tessellation. The tessellation circuit also includes shared tessellation logic that is controlled by the control logic, and includes a plurality of shared logic units, such as arithmetic logic units, that are controllable by the control logic based on the type of tessellation detected to be used for the incoming primitive. The shared tessellation logic is controlled to reuse at least some of the logic units for two different tessellation operations defined by the tessellation type information.

Abstract: A method, computer program product, and system are provided for processing data in a graphics pipeline. An embodiment of the method includes processing one or more vertices of a geometric primitive with a vertex shader function and generating new primitive information for the one or more processed vertices with a geometry shader function. The geometry shader function receives one or more processed vertices from the vertex shader function and emits a single vertex associated with the new primitive information. Each emitted vertex from the geometry shader function can be stored in a memory device. Unlike conventional graphic pipelines that require a memory device for data storage during the vertex and geometry shading processes, the present invention increases efficiency in the graphics pipeline by eliminating the need to access memory when the vertex and geometry shaders process vertex information.

Abstract: A method, system, and computer program product are disclosed for providing tessellated primitive data to a geometry shader. The method comprises computing a set of tessellated vertices and a computed set of connectivity data based on an original set of vertices and an original set of connectivity data, generating computed vertex data based on the original set of vertices and the set of tessellated vertices, receiving the computed set of connectivity data, requesting a subset of the computed vertex data based on the computed set of connectivity data, and processing primitives defined by the subset of the computed vertex data. The system and computer program product are further disclosed for accomplishing a similar result as the aforementioned method.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: Techniques for storing voicemails in real-time in a caller's voicemail system when a voicemail is left in a callee's voicemail system are provided. A connection to the callee's voicemail system is detected during a call from the caller to the callee. When a voicemail is being left on the caller's voicemail system, a copy of the voicemail message is automatically forked to the caller's voicemail system. Thus, when a voicemail message is recorded on the callee's voicemail system, a copy of the voicemail message is also stored on the caller's voicemail system.

Abstract: A conferencing system and method includes, during the conference session, invoking an interactive voice response (IVR) routine that provides names of one or more conference participants to a user of an audio-only endpoint device responsive to a request from the user to create a sidebar session. An invitation to join the sidebar session is then communicated to each of one or more participants selected by the user, the invitation being communicated via a private media channel separate from a media stream associated with the conference session. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A method and apparatus for performing tessellation lighting operations for video graphics primitives in a video graphics system is presented. When the vertex parameters corresponding to the vertices of a video graphics primitive are received, a tessellation operation is performed such that a number of component primitives are generated. The vertex parameters corresponding to the vertices of the component primitives are then calculated utilizing the vertex parameters for the original video graphics primitive. Such calculation operations include determining a corresponding normal vector for each component primitive vertex. Each of the component primitives is then individually processed. Such processing may include calculating the lighting effects for each component primitive and performing additional processing operations that generate pixel fragments for the primitive.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: A hardware tessellation circuit serves as a unified hardware parametric coordinate generator for providing parametric coordinates for tessellation. The tessellation circuit includes control logic that receives tessellation instruction information, such as an instruction indicating which type of multiple tessellation operations to perform, on an incoming primitive wherein the different types of tessellation include discrete tessellation, continuous tessellation and adaptive tessellation. The tessellation circuit also includes shared tessellation logic that is controlled by the control logic, and includes a plurality of shared logic units, such as arithmetic logic units, that are controllable by the control logic based on the type of tessellation detected to be used for the incoming primitive. The shared tessellation logic is controlled to reuse at least some of the logic units for two different tessellation operations defined by the tessellation type information.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: A method and apparatus for processing non-planar video graphics primitives is presented. Vertex parameters corresponding to vertices of a video graphics primitive are received, where the video graphics primitive is a non-planar, or higher-order, video graphics primitive. A cubic Bezier control mesh is calculated using the vertex parameters provided for the non-planar video graphics primitive. Two techniques for calculating control points included in the cubic Bezier control mesh along the edges of the non-planar video graphics primitive are described. The central control point is determined based on the average of a set of reflected vertices, where each of the reflected vertices is a vertex of the non-planar video graphics primitive reflected through a line defined by a pair of control points corresponding to the vertex.

Abstract: Tessellation triangles, which are used to model three-dimensional surfaces in computer-generated graphics, can be more efficiently calculated by retrieving tessellation triangle vertices and Bezier-function coefficients using a single, two-part address.

Abstract: An apparatus for processing a non-planar graphics primitive employs an associated method of operation and includes a controller, at least one computation engine, memory and at least one lookup table. Responsive to operation codes issued by the controller, the computation engine(s) determines a group of control points based on the position coordinates and normal vectors of the non-planar primitive vertices. The computation engine(s) then determines position coordinates of supplemental vertices defining multiple planar tessellated primitives based on the control points and stored weighting factors that provide a cubic relation between the control points and the position coordinates of the supplemental vertices. A first memory stores at least the control points and at least one lookup table stores the cubic weighting factors.

Abstract: There is provided a method for compressing texture values comprising: assigning texture values in a YUV format; packing the texture values into 32-bit words; and color promoting the texture values to 8-bit values. The YUV format has a Y component for every pixel sample, and U/V (they are also named Cr and Cb) components for every fourth sample. Every U/V sample coincides with four (2×2) Y samples. A single 32-bit word contains four packed Y values, one value each for U and V, and optionally four one-bit Alpha components as follows: YUV_0566-5-bits each of four Y values, 6-bits each for U and V; and YUV_1544-5-bits each of four Y values, 4-bits each for U and V, four 1-bit Alphas. The color promotion converts these components from 4-, 5-, or 6-bit values to 8-bit values. This method yields compression from 96 bits down to 32 bits, or 3:1 compression.

Abstract: In accordance with the present invention, the rate of change of texture addresses when mapped to individual pixels of a polygon is used to obtain the correct level of detail (LOD) map from a set of prefiltered maps. The method comprises a first determination of perspectively correct texture address values found at four corners of a predefined span or grid of pixels. Then, a linear interpolation technique is implemented to calculate a rate of change of texture addresses for pixels between the perspectively bound span corners. This linear interpolation technique is performed in both screen directions to thereby create a level of detail value for each pixel. The YUV formats described above have Y components for every pixel sample, and UN (they are also named Cr and Cb) components for every fourth sample. Every UN sample coincides with four (2×2) Y samples. This is identical to the organization of texels in U.S. Pat. No.

Abstract: In accordance with the present invention, the rate of change of texture addresses when mapped to individual pixels of a polygon is used to obtain the correct level of detail (LOD) map from a set of prefiltered maps. The method comprises a first determination of perspectively correct texture address values found at four corners of a predefined span or grid of pixels. Then, a linear interpolation technique is implemented to calculate a rate of change of texture addresses for pixels between the perspectively bound span corners. This linear interpolation technique is performed in both screen directions to thereby create a level of detail value for each pixel. The YUV formats described above have Y components for every pixel sample, and UN (they are also named Cr and Cb) components for every fourth sample. Every UN sample coincides with four (2×2) Y samples. This is identical to the organization of texels in U.S. Pat. No.