Patents by Inventor Vineet Goel

Vineet Goel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030016217
    Abstract: A method and apparatus for processing non-planar video graphics primitives is presented. Vertex parameters corresponding to vertices of a video graphics primitive are received, where the video graphics primitive is a non-planar, or higher-order, video graphics primitive. A cubic Bezier control mesh is calculated using the vertex parameters provided for the non-planar video graphics primitive. Two techniques for calculating control points included in the cubic Bezier control mesh along the edges of the non-planar video graphics primitive are described. The central control point is determined based on the average of a set of reflected vertices, where each of the reflected vertices is a vertex of the non-planar video graphics primitive reflected through a line defined by a pair of control points corresponding to the vertex.
    Type: Application
    Filed: May 10, 2001
    Publication date: January 23, 2003
    Inventors: Alexander C. Vlachos, Vineet Goel
  • Publication number: 20030011595
    Abstract: An apparatus for processing a non-planar graphics primitive employs an associated method of operation and includes a controller, at least one computation engine, memory and at least one lookup table. Responsive to operation codes issued by the controller, the computation engine(s) determines a group of control points based on the position coordinates and normal vectors of the non-planar primitive vertices. The computation engine(s) then determines position coordinates of supplemental vertices defining multiple planar tessellated primitives based on the control points and stored weighting factors that provide a cubic relation between the control points and the position coordinates of the supplemental vertices. A first memory stores at least the control points and at least one lookup table stores the cubic weighting factors.
    Type: Application
    Filed: May 10, 2001
    Publication date: January 16, 2003
    Inventors: Vineet Goel, Robert S. Hartog, Michael A. Mang
  • Publication number: 20020167523
    Abstract: In accordance with the present invention, the rate of change of texture addresses when mapped to individual pixels of a polygon is used to obtain the correct level of detail (LOD) map from a set of prefiltered maps. The method comprises a first determination of perspectively correct texture address values found at four corners of a predefined span or grid of pixels. Then, a linear interpolation technique is implemented to calculate a rate of change of texture addresses for pixels between the perspectively bound span corners. This linear interpolation technique is performed in both screen directions to thereby create a level of detail value for each pixel. The YUV formats described above have Y components for every pixel sample, and UN (they are also named Cr and Cb) components for every fourth sample. Every UN sample coincides with four (2×2) Y samples. This is identical to the organization of texels in U.S. Pat. No.
    Type: Application
    Filed: October 16, 2001
    Publication date: November 14, 2002
    Inventors: Ralph Clayton Taylor, Michael Mantor, Vineet Goel, Val Gene Cook, Stuart Krupnik
  • Patent number: 6211883
    Abstract: A high order surface patch rendering system with adaptive tessellation. A patch is rendered by subdividing a patch until the subpatches are sufficiently flat that they can be approximated by a quadrilateral. To determine when a subpatch is flat enough to be approximated with a quadrilateral, the patch rendering system uses a patch flatness test unit which tests the straightness of the edges and internal curves of the subpatch. The edges and internal curves of a subpatch are determined to be straight if the intermediate control points of a curve are within a tolerance range of a straight line between the curve's endpoints. The tolerance range is chosen with respect to a pixel resolution of the final image so that subpatch is determined to be flat when the curvature of the subpatch cannot be perceived relative to a flat surface. One embodiment contemplates a flatness test unit for determining the flatness of a patch having a set of control points. The flatness test unit comprises a series of stages.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: April 3, 2001
    Assignee: LSI Logic Corporation
    Inventor: Vineet Goel
  • Patent number: 6100894
    Abstract: A high order surface patch rendering system with adaptive tessellation. A patch is rendered by subdividing a patch until the subpatches are sufficiently flat that they can be approximated by a quadrilateral. To subdivide a patch, the patch rendering system uses a patch division unit which accepts the control points of a patch and divides the patch in half by determining the control points of a subpatch. The relationship of the patch to it's subpatches is that of a binary tree, where every patch division produces two subpatches which may themselves be subject to patch division. In one embodiment, the patch division unit is able to traverse the binary subdivision tree in three directions (parent to left-child, left-child to right-sibling, and right-sibling to parent) to minimize memory requirements. In this embodiment the patch division unit comprises a set of curve division units.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: August 8, 2000
    Assignee: LSI Logic Corporation
    Inventor: Vineet Goel
  • Patent number: 6057848
    Abstract: A high order surface patch rendering system. A patch is rendered by subdividing a patch until the subpatches are sufficiently flat that they can be approximated by a quadrilateral, which can then be split diagonally and written to a rasterizer in the form of two triangles. In one embodiment, the patch rendering system receives rational coordinates (X,Y,Z,W) and attribute coordinates (color, opacity, texture) of control points of the Bezier surface patch. The patch rendering system divides and subdivides the surface patch by operating on the surface patch control points to produce subpatch control points. The rational coordinates of the control points are converted to spatial coordinates, and if the current subpatch is determined to be flat, the spatial coordinates and attributes of the subpatch corner points are provided to an output buffer in the form of triangle vertices with associated attributes.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: May 2, 2000
    Assignee: LSI Logic Corporation
    Inventor: Vineet Goel
  • Patent number: 5999188
    Abstract: The present invention addresses the problem of describing an arbitrary object (up to user-defined limits) given a set of triangles with vertex normals describing the object. A novel method of successively merging traingles into larger and larger patches to compute a set of "as-few-as-possible" Bezier patches is presented. This method is not only applicable to arbitrary objects, but also aims at producing as few patches as possible depending on the geometry of the input object. Also presented are methods to enforce C.sup.0 - and C.sup.1 -continuity between a pair of patches B.sub.L (s,t) and B.sub.R (s,t), placed arbitrarily. The methods perturb the appropnate control points to achieve geometric continuities. For C.sup.0 -continuity the area of the hole between the patches is minimized by formulating the area as a series of linear programs, where the continuity has to be enforced across the adjacent boundary curves B.sub.L (1,t) and B.sub.R (0,t). Similarly, to enforce C.sup.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: December 7, 1999
    Assignee: LSI Logic Corporation
    Inventors: Nishit Kumar, Vineet Goel, Leonardo Vainsencher
  • Patent number: 5995109
    Abstract: A method for efficient, high quality rendering of a surface patch. The method tests a surface patch for flatness, and if the surface patch is not flat, the method divides the surface patch into a left surface patch and a right surface patch. Otherwise if the surface patch is flat, the method converts the surface patch into triangles. This method can be implemented to operate recursively, thereby ensuring that all portions of the patch are eventually converted into triangles when the portions become small enough to satisfy the flatness condition. A patch tests as flat only if all curves which form the patch do not deviate from straight lines by more than a predetermined tolerance. The division is efficiently performed by determining (i) left patch control points for a first portion of all curves along one axis of the surface patch, and (ii) right patch control points for a second portion of all curves along said axis of the surface patch.
    Type: Grant
    Filed: April 8, 1997
    Date of Patent: November 30, 1999
    Assignee: LSI Logic Corporation
    Inventors: Vineet Goel, Leonardo Vainsencher