Abstract: A system includes a memory array of sub-blocks, each sub-block including groups of memory cells, and a processing device. The processing device causes a first wordline to be programmed through the sub-blocks with a mask by causing to be programmed, to a first voltage level: a first group of memory cells of a first sub-block; and a second group of memory cells of a second sub-block. The processing device further scans a second wordline that has been programmed and is coupled to the first wordline, scanning includes: causing a custom wordline voltage to be applied to the second wordline, the custom wordline voltage to select groups of memory cells corresponding to those of the first wordline programmed to the first voltage level; concurrently reading data from the selected groups of memory cells of the second wordline; and performing, using the data, an error check of the second wordline.

Abstract: Power consumption of sensing circuitry in a NAND Flash device is reduced by reducing the voltage supply to a portion of logic circuits in sensing circuitry. A first power domain provides power to a first portion of the logic circuits in the sensing circuity and a second power domain provides power to a second portion of the logic circuits in the sensing circuitry. The first power domain has a higher voltage than the second power domain.

Abstract: A memory device comprises an array of memory cells organized into a plurality of wordlines, and a processing device to perform processing operations that receive a program command specifying a memory unit and data comprising first received data, where the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines. The processing operations also program the specified data to the memory unit by programming the first received data to the one or more first active data wordlines, identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines, generating a first data pattern comprising a first plurality of threshold voltage levels, and programming the first data pattern to the first retired boundary wordline.

Abstract: Control logic in a memory device selects two or more blocks of a plurality of blocks to concurrently scan during a scan operation. The control logic can further cause a first voltage to be applied to a dummy word line of each block of the two or more blocks to selectively couple a string of memory cells in each block of the two or more blocks to a different sense amplifier of a set of sense amplifiers coupled with the plurality of blocks. The control logic can cause a second voltage to be applied to a selected word line of each block of the two or more blocks to read a bit stored at a respective memory cell of the string of memory cells in each block out to the set of sense amplifier.

Abstract: A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and a circuit coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element.

Abstract: The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.

Abstract: A memory device includes a memory array of memory cells. A page buffer is to apply, to a bit line, a first voltage or a second voltage that is higher than the first voltage during a program verify operation. Control logic operatively coupled with the page buffer is to perform operations including: causing a plurality of memory cells to be programmed with a first program pulse; measuring a threshold voltage for the memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, a first subset of the memory cells as having a faster quick charge loss than that of a second subset of the memory cells; and causing, in response to the classifying, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells.

Abstract: A memory device includes an array of memory cells arranged in sub-blocks. Memory cells of a sub-block are coupled to a pillar of the array and are associated with multiple wordlines. To perform a read operation, control logic coupled with the array performs operations including: tracking a length of time that a selected wordline takes to reach a pass voltage before being able to read data from a memory cell associated with the selected wordline; in response to the length of time satisfying a first threshold criterion, causing a first delay time to pass before reading the data; and in response to the length of time satisfying a second threshold criterion that is longer than the first threshold criterion, causing a second delay time to pass before reading the data, the second delay time being longer than the first delay time.

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a set of commands to concurrently program a set of cells of the memory array with dummy data, the set of cells corresponding to a group of retired wordlines of the plurality of wordlines, in response to receiving the set of commands, obtaining the dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.

Abstract: Described are systems and methods for validating read level voltage in memory devices. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a read level voltage to be applied to a specified wordline of the plurality of wordlines; receiving an actual bit count reflecting a number of memory cells that have their respective threshold voltages below the read level voltage; and responsive to determining that a difference of an expected bit count and the actual bit count exceeds a predetermined threshold value, adjusting the read level voltage.

Abstract: A memory sub-system configured to improve performance using signal and noise characteristics of memory cells measured during the execution of a command in a memory component. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing the command in the memory component. A processing device separate from the memory component transmits the command to the memory component, and receives and processes the signal and noise characteristics to identify an attribute about the memory component. Subsequently, an operation related to data stored in the memory component can be performed based on the attribute.

Abstract: A method includes receiving, by control logic of a memory device, a copyback clear command from a processing device; causing, in response to the copyback clear command, a page buffer to perform a dual-strobe read operation on first memory cells configured as single-level cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage that are sensed between threshold voltage distributions of the first memory cells; causing the page buffer to determine a number of one bit values within the threshold voltage distributions detected in a threshold voltage range between the first/second threshold voltages; and causing, in response to the number of one bit values not satisfying a threshold criterion, a copyback of data in the first memory cells to second memory cells configured as high-level cells without intervention from the processing device.

Abstract: A memory device comprising an array of memory cells organized into a set of sub-blocks and a set of wordlines. Control logic is operatively coupled with the array of memory cells, the control logic to perform operations including: receiving a program command from a processing device, the program command including information indicative of a physical address associated with a retired wordline of the set of wordlines; in response to detecting the information within the program command, generating dummy data that is one of pseudo-random data, all one values, or all zero values; and causing the dummy data to be programmed to memory cells of multiple sub-blocks of the set of sub-blocks that are selectively connected to the retired wordline.

Abstract: A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled to the array of memory cells. The control logic performs operations including: causing hardware initialization of a set of sub-blocks that are to be programmed within the array of memory cells; causing a first sub-block of the set of sub-blocks to be preconditioned for a program operation; causing multiple pages of data to be programmed to respective ones of the set of sub-blocks; and selectively causing a program verify to be performed on memory cells of the set of sub-blocks after programming the multiple pages of data.

Abstract: A memory device to calibrate voltages used to read a group of memory cells. For example, the memory device measures first signal and noise characteristics of a group of memory cells by reading the group of memory cells at first test voltages that are separated from each other by a first voltage interval. An estimate of a read level of the group of memory cells is determined based on the first signal and noise characteristics. The memory device then measures second signal and noise characteristics of the group of memory cells by reading the group of memory cells at second test voltages that are separated from each other by a second voltage interval that is smaller than the first voltage interval. An optimized read voltage for the read level is computed from the second signal and noise characteristics.

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

Abstract: An apparatus includes circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.

Abstract: A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses.

Abstract: Described are systems and methods for implementing continuous memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array.