Abstract: Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.

Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining first states of a first sense node and a second sense node while a first voltage level is capacitively coupled to the first sense node and while a second voltage level is capacitively coupled to the second sense node, determining a second states of the first and second sense nodes while a third voltage level is capacitively coupled to the first sense node and while a fourth voltage level is capacitively coupled to the second sense node, determining a fifth voltage level in response to at least the first states of the first and second sense nodes and the second states of the first and second sense nodes, and determining third states of the first and second sense nodes while the fifth voltage level is capacitively coupled to the first and second sense nodes.

Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining first states of a first sense node and a second sense node while a first voltage level is capacitively coupled to the first sense node and while a second voltage level is capacitively coupled to the second sense node, determining a second states of the first and second sense nodes while a third voltage level is capacitively coupled to the first sense node and while a fourth voltage level is capacitively coupled to the second sense node, determining a fifth voltage level in response to at least the first states of the first and second sense nodes and the second states of the first and second sense nodes, and determining third states of the first and second sense nodes while the fifth voltage level is capacitively coupled to the first and second sense nodes.

Abstract: A memory device includes a plurality of data lines, a common source, and control logic. The control logic is configured to implement a seed operation by biasing each of the plurality of data lines to a first voltage level with the common source biased to a second voltage level lower than the first voltage level. With each data line biased to the first voltage level, the control logic is configured to float each data line and bias the common source to the first voltage level such that the bias of each data line is boosted above the first voltage level due to capacitive coupling between each data line and the common source.

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.

Abstract: Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.

Abstract: In one example, a nonvolatile memory device, such as a NAND flash memory device, includes an array of non-volatile memory cells. Program operations performed by the memory may be suspended (e.g., in order to service a high priority read request). The memory device includes a timer to track a duration of time the program operation is suspended. Upon program resume, the controller applies a program voltage after resume that is adjusted based on the duration of time the program operation is suspended.

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.

Abstract: A memory device includes a plurality of data lines, a common source, and control logic. The control logic is configured to implement a seed operation by biasing each of the plurality of data lines to a first voltage level with the common source biased to a second voltage level lower than the first voltage level. With each data line biased to the first voltage level, the control logic is configured to float each data line and bias the common source to the first voltage level such that the bias of each data line is boosted above the first voltage level due to capacitive coupling between each data line and the common source.

Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator is readable. Responsive to determining that the status indicator readable, it can be determined that programming of data to the data block of the memory component did complete and there is a data retention loss.

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.

Abstract: A method for reading an array of memory cells includes enabling a current to flow through even data lines of the array of memory cells. The method includes blocking a current from flowing through odd data lines of the array of memory cells. The method includes sensing data stored in memory cells coupled to the even data lines.

Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell.

Abstract: The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.

Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

Abstract: A memory device includes a plurality of data lines, a common source, and control logic. The control logic is configured to implement a seed operation by biasing each of the plurality of data lines to a first voltage level with the common source biased to a second voltage level lower than the first voltage level. With each data line biased to the first voltage level, the control logic is configured to float each data line and bias the common source to the first voltage level such that the bias of each data line is boosted above the first voltage level due to capacitive coupling between each data line and the common source.

Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator can be read. Responsive to determining that the status indicator cannot be read, it can be determined that programming of data to the data block of the memory component did not complete based on a prior loss of power to the memory component.

Abstract: Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.

Abstract: The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.