Patents by Inventor Vishal Anand
Vishal Anand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200073979Abstract: A method for validating data in a hybrid cloud model that includes providing a validation layer in the brokerage module of the hybrid architecture. The validation layer is separate from an applications layer of the hybrid architecture. The method includes sending target object values to a centralized brokerage layer composite query generator (BLCQG) component of the validation layer from an application needing validation of target data time. The method continues with generating a composite validation rule set with the brokerage layer composite query generator (BLCQG) component based on the parameters of the target object values. The method further includes validating the target data item of the target object values with the composite validation rule in the validation rules validator (VRV) component; and sending the target data item that has been validated to the application.Type: ApplicationFiled: September 5, 2018Publication date: March 5, 2020Inventors: Santanu Bandyopadhyay, Ramesh Chandra Pathak, Suryanarayana Rao, Vishal Anand
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Patent number: 10579573Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.Type: GrantFiled: May 2, 2018Date of Patent: March 3, 2020Assignee: Cavium, LLCInventors: Guy Townsend Hutchison, Harish Krishnamoorthy, Gerald Schmidt, Vishal Anand
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Patent number: 10560399Abstract: Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip. Each pipe on the network chip implements a dynamic port renumbering scheme that dynamically assigns a relative port number for each port assigned to that pipe. The dynamic port renumbering scheme allows for internal parallelism without increasing the total amount of state space required for the ports on the network chip.Type: GrantFiled: July 18, 2017Date of Patent: February 11, 2020Assignee: Cavium, LLCInventors: Vishal Anand, Vamsi Panchagnula
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Publication number: 20200019286Abstract: An approach is provided for monitoring disk utilization at an object level. At a first time a first size of an object in a System i computing platform is determined by calling an application programming interface (API). At a second time a second size of the object is determined by calling the API. A difference between the first and second sizes is determined. The difference is determined to be greater than a threshold. Based on the difference exceeding the threshold, an alert is sent indicating growth at the object level rather than at an auxiliary storage pool level. The API is called to obtain the sizes of libraries in the System i computing platform. Differences between the sizes of the libraries at a user-entered start date and the current time are determined and presented. A report including the differences is generated and sent.Type: ApplicationFiled: September 26, 2019Publication date: January 16, 2020Inventors: Vishal Anand, Sahadev Dey, Rajneesh Kumar, Vijay S. Patil, Amit Patra
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Patent number: 10496248Abstract: An approach is provided for monitoring disk utilization at an object level. At a first time a first size of an object in a System i computing platform is determined by calling an application programming interface (API). At a second time a second size of the object is determined by calling the API. A difference between the first and second sizes is determined. The difference is determined to be greater than a threshold. Based on the difference exceeding the threshold, an alert is sent indicating growth at the object level rather than at an auxiliary storage pool level. The API is called to obtain the sizes of objects in an integrated file system in the System i computing platform. Differences between the sizes of the objects at a user-entered start date and the current time are determined and presented. A report including the differences is generated and sent.Type: GrantFiled: August 13, 2018Date of Patent: December 3, 2019Assignee: International Business Machines CorporationInventors: Vishal Anand, Sahadev Dey, Rajneesh Kumar, Vijay S. Patil, Amit Patra
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Publication number: 20190312432Abstract: A method and apparatus for parallel operation of multiple power sources including one fuel cell power source. The apparatus includes a droop controller master communicatively connected to the multiple power sources and configured to measure a load demand for the multiple power sources, a first droop controller slave communicatively connected to the droop controller master and to a first fuel cell power source, the first droop controller configured to calculate a first droop profile for the first fuel cell power source, a second droop controller slave communicatively connected to the droop controller master and to a second power source, and a first inverter, electrically connected to the first fuel cell power source and communicatively connected to the first droop controller slave, and configured to output power according to a first droop profile.Type: ApplicationFiled: April 4, 2018Publication date: October 10, 2019Inventors: Ranganathan GURUNATHAN, Arne BALLANTINE, Prasad PMSVVSV, Vishal Anand GOPALAKRISHNAN, Saravanakumar NARAYANASAMY, Badrinarayanan THIRUVENGADASWAMY
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Patent number: 10397113Abstract: Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived at. The packets can be distributed for processing within the network chip.Type: GrantFiled: March 13, 2017Date of Patent: August 27, 2019Assignee: Cavium, LLCInventors: Vishal Anand, Tsahi Daniel, Gerald Schmidt, Premshanth Theivendran
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Publication number: 20190180266Abstract: A method of operating a distributed peer to peer analytics system of a permissioned distributed ledger is provided. The system includes a plurality of node computing devices in operable communication with each other over an electronic network. The method includes capturing, by a merchant computing device, sales data from a payment transaction, storing the captured sales data in a database of a first node, compiling within the first node the stored sales data into a transaction envelope, encrypting the transaction envelope with a private key of the first node, submitting, by the first node, the encrypted envelope to the permissioned distributed ledger, verifying, by a second node, the submitted encrypted envelope and adding the compiled sales data to a data block, committing, by the second node, the data block to the distributed ledger, and validating, by a consensus of the plurality of node computing devices, the committed data block.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Inventors: Navjot S. Sidhu, Vishal Anand, Ryan Senci
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Patent number: 10268464Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.Type: GrantFiled: July 7, 2017Date of Patent: April 23, 2019Assignee: Intel CorporationInventors: Daniel P. Daly, Thomas E. Willis, Pat Wang, Vishal Anand, Hung Nguyen, Varsha Apte
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Publication number: 20190112946Abstract: A service tube for a gas turbine engine includes an entry end fitting; an exit end fitting; and a housing that interconnects the entry end fitting and the exit end fitting to define an annulus around an oil tube.Type: ApplicationFiled: October 13, 2017Publication date: April 18, 2019Inventors: Peter S. Matteson, Ravi K. Madabhushi, Rajendra Prasad Parimala, Vishal Anand
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Publication number: 20190052661Abstract: A computer-implemented method of fraud detection comprising receiving a user identification, a standard authentication key, and an alternative authentication key associated with a user. The method includes storing the standard and alternative authentication keys in a user profile associated with the user identification, and storing a contingent action corresponding to the alternative authentication key. The method includes receiving an authorization request including the user identification and an authentication input, and comparing the authentication input with the standard authentication key and the alternative authentication key in the user profile. The method includes determining that the authentication input matches the alternative authentication key. Based on the determination that the authentication input matches the alternative authentication key, the method includes initiating the contingent action stored in the user profile corresponding to the alternative authentication key.Type: ApplicationFiled: August 10, 2017Publication date: February 14, 2019Inventor: Vishal Anand
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Publication number: 20190012156Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.Type: ApplicationFiled: July 7, 2017Publication date: January 10, 2019Inventors: Daniel P. Daly, Thomas E. Willis, Pat Wang, Vishal Anand, Hung Nguyen, Varsha Apte
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Publication number: 20180348973Abstract: An approach is provided for monitoring disk utilization at an object level. At a first time a first size of an object in a System i computing platform is determined by calling an application programming interface (API). At a second time a second size of the object is determined by calling the API. A difference between the first and second sizes is determined. The difference is determined to be greater than a threshold. Based on the difference exceeding the threshold, an alert is sent indicating growth at the object level rather than at an auxiliary storage pool level. The API is called to obtain the sizes of objects in an integrated file system in the System i computing platform. Differences between the sizes of the objects at a user-entered start date and the current time are determined and presented. A report including the differences is generated and sent.Type: ApplicationFiled: August 13, 2018Publication date: December 6, 2018Inventors: Vishal Anand, Sahadev Dey, Rajneesh Kumar, Vijay S. Patil, Amit Patra
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Patent number: 10078605Abstract: Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip.Type: GrantFiled: October 22, 2014Date of Patent: September 18, 2018Assignee: Cavium, Inc.Inventors: Vishal Anand, Harish Krishnamoorthy, Guy Townsend Hutchison, Gerald Schmidt
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Patent number: 10073594Abstract: An approach is provided for monitoring disk utilization at an object level. At a first time a first size of an object (i.e., integrated file system or library) in a System i computing platform is determined. At a second time a second size of the object is determined. A difference between the first and second sizes is determined. The difference is determined to be greater than a threshold. Based on the difference exceeding the threshold, an alert is sent indicating growth at the object level rather than at an auxiliary storage pool level. Sizes of System i libraries are monitored at multiple dates and stored in a repository. Sizes of the libraries at user-entered start and end dates are retrieved from the repository. Differences between the sizes of the libraries at the start and end dates are determined and presented.Type: GrantFiled: October 23, 2017Date of Patent: September 11, 2018Assignee: International Business Machines CorporationInventors: Vishal Anand, Sahadev Dey, Rajneesh Kumar, Vijay S. Patil, Amit Patra
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Publication number: 20180246836Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.Type: ApplicationFiled: May 2, 2018Publication date: August 30, 2018Inventors: Guy Townsend Hutchison, Harish Krishnamoorthy, Gerald Schmidt, Vishal Anand
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Patent number: 10050833Abstract: Embodiments of the apparatus for reducing latency in a flexible parser relate to an implementation that optimizes each parser engine within the parser. A packet enters the parser. Each of the parser engines processes the packet if processing is required. Otherwise, the parser engine simply forwards the packet through without processing the packet, thereby reducing latency. Each parser engine includes a memory. The memory stores bypass data and status information that indicates whether parsing for this packet is completed and, thus, no further processing is required by subsequent parser engines. Each parser engine also includes a counter, which is incremented whenever a packet enters the parser engine and is decremented whenever a packet exists the parser engine. A packet bypasses the parser engine based on the counter of the parser engine and the status information of that packet.Type: GrantFiled: June 19, 2014Date of Patent: August 14, 2018Assignee: Cavium, Inc.Inventors: Vishal Anand, Tsahi Daniel, Gerald Schmidt
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Patent number: 10007604Abstract: A method and apparatus for implementing a storage optimization process is provided. The method includes identifying a file for storage on a storage device. The storage device determines that the file comprises a file size that exceeds multiple physical disk blocks of the storage device by a fractional value. The file is divided into a first portion and a second portion. The first portion comprises a file size such that the first portion fits entirely within a first single block of the storage device. The second portion comprises a size such that the second portion exceeds a size of a second single block of the storage device by the fractional value. The first portion is stored within the first single block. The second portion is compressed such that a resulting compressed file fits entirely within the second single block.Type: GrantFiled: January 3, 2017Date of Patent: June 26, 2018Assignee: International Business Machines CorporationInventor: Vishal Anand
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Patent number: 9990324Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.Type: GrantFiled: October 22, 2014Date of Patent: June 5, 2018Assignee: Cavium Inc.Inventors: Guy Townsend Hutchison, Harish Krishnamoorthy, Gerald Schmidt, Vishal Anand
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Patent number: 9961167Abstract: Embodiments of the apparatus for modifying packet headers relate to a rewrite engine that represents each protocol header of packets in a generic format specific to that protocol to enable programmable modifications of packets, resulting in hardware and software flexibility in modifying packet headers. Software programs generic formats in a hardware table for various protocols. The rewrite engine is able to detect missing fields from a protocol header and is able to expand the protocol header to a maximum size such that the protocol header contains all possible fields of that protocol. Each of the fields has the same offset irrespective of which variation of the protocol the protocol header corresponds to. In a bit vector, all newly added fields are marked invalid (represented by 0), and all existing fields are marked valid (represented by 1). Software modification commands allow data to be replaced, removed and inserted.Type: GrantFiled: June 19, 2014Date of Patent: May 1, 2018Assignee: Cavium, Inc.Inventors: Chirinjeev Singh, Vishal Anand, Tsahi Daniel, Gerald Schmidt