Patents by Inventor Vishal Anand

Vishal Anand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190012156
    Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.
    Type: Application
    Filed: July 7, 2017
    Publication date: January 10, 2019
    Inventors: Daniel P. Daly, Thomas E. Willis, Pat Wang, Vishal Anand, Hung Nguyen, Varsha Apte
  • Publication number: 20180348973
    Abstract: An approach is provided for monitoring disk utilization at an object level. At a first time a first size of an object in a System i computing platform is determined by calling an application programming interface (API). At a second time a second size of the object is determined by calling the API. A difference between the first and second sizes is determined. The difference is determined to be greater than a threshold. Based on the difference exceeding the threshold, an alert is sent indicating growth at the object level rather than at an auxiliary storage pool level. The API is called to obtain the sizes of objects in an integrated file system in the System i computing platform. Differences between the sizes of the objects at a user-entered start date and the current time are determined and presented. A report including the differences is generated and sent.
    Type: Application
    Filed: August 13, 2018
    Publication date: December 6, 2018
    Inventors: Vishal Anand, Sahadev Dey, Rajneesh Kumar, Vijay S. Patil, Amit Patra
  • Patent number: 10078605
    Abstract: Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: September 18, 2018
    Assignee: Cavium, Inc.
    Inventors: Vishal Anand, Harish Krishnamoorthy, Guy Townsend Hutchison, Gerald Schmidt
  • Patent number: 10073594
    Abstract: An approach is provided for monitoring disk utilization at an object level. At a first time a first size of an object (i.e., integrated file system or library) in a System i computing platform is determined. At a second time a second size of the object is determined. A difference between the first and second sizes is determined. The difference is determined to be greater than a threshold. Based on the difference exceeding the threshold, an alert is sent indicating growth at the object level rather than at an auxiliary storage pool level. Sizes of System i libraries are monitored at multiple dates and stored in a repository. Sizes of the libraries at user-entered start and end dates are retrieved from the repository. Differences between the sizes of the libraries at the start and end dates are determined and presented.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Vishal Anand, Sahadev Dey, Rajneesh Kumar, Vijay S. Patil, Amit Patra
  • Publication number: 20180246836
    Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.
    Type: Application
    Filed: May 2, 2018
    Publication date: August 30, 2018
    Inventors: Guy Townsend Hutchison, Harish Krishnamoorthy, Gerald Schmidt, Vishal Anand
  • Patent number: 10050833
    Abstract: Embodiments of the apparatus for reducing latency in a flexible parser relate to an implementation that optimizes each parser engine within the parser. A packet enters the parser. Each of the parser engines processes the packet if processing is required. Otherwise, the parser engine simply forwards the packet through without processing the packet, thereby reducing latency. Each parser engine includes a memory. The memory stores bypass data and status information that indicates whether parsing for this packet is completed and, thus, no further processing is required by subsequent parser engines. Each parser engine also includes a counter, which is incremented whenever a packet enters the parser engine and is decremented whenever a packet exists the parser engine. A packet bypasses the parser engine based on the counter of the parser engine and the status information of that packet.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: August 14, 2018
    Assignee: Cavium, Inc.
    Inventors: Vishal Anand, Tsahi Daniel, Gerald Schmidt
  • Patent number: 10007604
    Abstract: A method and apparatus for implementing a storage optimization process is provided. The method includes identifying a file for storage on a storage device. The storage device determines that the file comprises a file size that exceeds multiple physical disk blocks of the storage device by a fractional value. The file is divided into a first portion and a second portion. The first portion comprises a file size such that the first portion fits entirely within a first single block of the storage device. The second portion comprises a size such that the second portion exceeds a size of a second single block of the storage device by the fractional value. The first portion is stored within the first single block. The second portion is compressed such that a resulting compressed file fits entirely within the second single block.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventor: Vishal Anand
  • Patent number: 9990324
    Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: June 5, 2018
    Assignee: Cavium Inc.
    Inventors: Guy Townsend Hutchison, Harish Krishnamoorthy, Gerald Schmidt, Vishal Anand
  • Patent number: 9961167
    Abstract: Embodiments of the apparatus for modifying packet headers relate to a rewrite engine that represents each protocol header of packets in a generic format specific to that protocol to enable programmable modifications of packets, resulting in hardware and software flexibility in modifying packet headers. Software programs generic formats in a hardware table for various protocols. The rewrite engine is able to detect missing fields from a protocol header and is able to expand the protocol header to a maximum size such that the protocol header contains all possible fields of that protocol. Each of the fields has the same offset irrespective of which variation of the protocol the protocol header corresponds to. In a bit vector, all newly added fields are marked invalid (represented by 0), and all existing fields are marked valid (represented by 1). Software modification commands allow data to be replaced, removed and inserted.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: May 1, 2018
    Assignee: Cavium, Inc.
    Inventors: Chirinjeev Singh, Vishal Anand, Tsahi Daniel, Gerald Schmidt
  • Publication number: 20180046332
    Abstract: An approach is provided for monitoring disk utilization at an object level. At a first time a first size of an object (i.e., integrated file system or library) in a System i computing platform is determined. At a second time a second size of the object is determined. A difference between the first and second sizes is determined. The difference is determined to be greater than a threshold. Based on the difference exceeding the threshold, an alert is sent indicating growth at the object level rather than at an auxiliary storage pool level. Sizes of System i libraries are monitored at multiple dates and stored in a repository. Sizes of the libraries at user-entered start and end dates are retrieved from the repository. Differences between the sizes of the libraries at the start and end dates are determined and presented.
    Type: Application
    Filed: October 23, 2017
    Publication date: February 15, 2018
    Inventors: Vishal Anand, Sahadev Dey, Rajneesh Kumar, Vijay S. Patil, Amit Patra
  • Publication number: 20170364920
    Abstract: One embodiment of the invention is directed to a computer-implemented method comprising, receiving an indication that an avatar of a user has initiated a transaction in a virtual reality environment. The method further comprises obtaining a first biometric sample from the user interacting with the virtual reality hardware. The method further comprises generating a partial biometric template based at least in part on the first biometric sample. The method further comprises providing the partial biometric template and personal authentication information for the avatar to an authentication computer where the personal authentication information and the partial biometric template are used to authenticate the avatar.
    Type: Application
    Filed: June 16, 2016
    Publication date: December 21, 2017
    Inventor: Vishal Anand
  • Patent number: 9823814
    Abstract: An approach is provided for monitoring disk utilization at an object level. At a first time a first size of an object in a System i computing platform is determined by calling an application programming interface (API). The object is an integrated file system object or a library that includes other objects in the System i platform. At a second time a second size of the object is determined by calling the API. A difference between the first and second sizes is determined. The difference is determined to be greater than a threshold. Based on the difference exceeding the threshold, an alert is sent. The alert indicates the object had a growth in size that exceeds the threshold and indicates the growth at a level of the object, which is different from a growth at a level of an auxiliary storage pool in the System i platform.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Vishal Anand, Sahadev Dey, Rajneesh Kumar, Vijay S. Patil, Amit Patra
  • Publication number: 20170317951
    Abstract: Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip. Each pipe on the network chip implements a dynamic port renumbering scheme that dynamically assigns a relative port number for each port assigned to that pipe. The dynamic port renumbering scheme allows for internal parallelism without increasing the total amount of state space required for the ports on the network chip.
    Type: Application
    Filed: July 18, 2017
    Publication date: November 2, 2017
    Inventors: Vishal Anand, Vamsi Panchagnula
  • Patent number: 9787549
    Abstract: A resource requirements method and system is provided. The method includes identifying dependencies and calculating a utilization value for a source server. The source server is mapped to an application and a source infrastructure is compared to a target infrastructure. Deficiencies and differences associated with the target infrastructure are determined and dependency requirements for fulfillment in the target infrastructure are generated. The utilization value is compared to a resource capability of the target server and resource requirements for fulfillment on the target server are generated.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventor: Vishal Anand
  • Patent number: 9742694
    Abstract: Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip. Each pipe on the network chip implements a dynamic port renumbering scheme that dynamically assigns a relative port number for each port assigned to that pipe. The dynamic port renumbering scheme allows for internal parallelism without increasing the total amount of state space required for the ports on the network chip.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: August 22, 2017
    Assignee: Cavium, Inc.
    Inventors: Vishal Anand, Vamsi Panchagnula
  • Publication number: 20170212834
    Abstract: A method and apparatus for implementing a storage optimization process is provided. The method includes identifying a file for storage on a storage device. The storage device determines that the file comprises a file size that exceeds multiple physical disk blocks of the storage device by a fractional value. The file is divided into a first portion and a second portion. The first portion comprises a file size such that the first portion fits entirely within a first single block of the storage device. The second portion comprises a size such that the second portion exceeds a size of a second single block of the storage device by the fractional value. The first portion is stored within the first single block. The second portion is compressed such that a resulting compressed file fits entirely within the second single block.
    Type: Application
    Filed: January 3, 2017
    Publication date: July 27, 2017
    Inventor: Vishal Anand
  • Publication number: 20170187623
    Abstract: Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived at. The packets can be distributed for processing within the network chip.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Inventors: Vishal Anand, Tsahi Daniel, Gerald Schmidt, Premshanth Theivendran
  • Patent number: 9628385
    Abstract: Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived at. The packets can be distributed for processing within the network chip.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: April 18, 2017
    Assignee: Cavium, Inc.
    Inventors: Vishal Anand, Tsahi Daniel, Gerald Schmidt, Premshanth Theivendran
  • Patent number: 9588694
    Abstract: A method and apparatus for implementing a storage optimization process is provided. The method includes identifying a file for storage on a storage device. The storage device determines that the file comprises a file size that exceeds multiple physical disk blocks of the storage device by a fractional value. The file is divided into a first portion and a second portion. The first portion comprises a file size such that the first portion fits entirely within a first single block of the storage device. The second portion comprises a size such that the second portion exceeds a size of a second single block of the storage device by the fractional value. The first portion is stored within the first single block. The second portion is compressed such that a resulting compressed file fits entirely within the second single block.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: March 7, 2017
    Assignee: International Business Machines Corporation
    Inventor: Vishal Anand
  • Patent number: 9542342
    Abstract: A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is finished updating the holding register and the holding register is ready to commit to the target register, a source identifier is added to a register bus. The source identifier identifies the holding register as the originator of the transaction on the register bus. The N holding registers are able to simultaneously handle N register transactions. The max value of N is 2n, where n is the number of bits in the source identifier.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: January 10, 2017
    Assignee: Cavium, Inc.
    Inventors: Vishal Anand, Harish Krishnamoorthy, Guy Townsend Hutchison