Abstract: An approach is provided for monitoring disk utilization at an object level. At a first time a first size of an object in a System i computing platform is determined by calling an application programming interface (API). The object is an integrated file system object or a library that includes other objects in the System i platform. At a second time a second size of the object is determined by calling the API. A difference between the first and second sizes is determined. The difference is determined to be greater than a threshold. Based on the difference exceeding the threshold, an alert is sent. The alert indicates the object had a growth in size that exceeds the threshold and indicates the growth at a level of the object, which is different from a growth at a level of an auxiliary storage pool in the System i platform.

Abstract: A method includes controlling multiple networked input-parallel/output-parallel inverters of a fuel cell system as a single inverter assembly by a master controller. A fuel cell system includes a plurality of fuel cell segments, a plurality of DC/DC converters and at least one DC/AC inverter, where an output of each of the plurality of the fuel cell segments is connected to a pair of DC/DC converters, and each of the pair DC/DC converters is connected to an opposite polarity bus being provided to the inverter.

Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

Abstract: An error detection circuit on a semiconductor chip detects whether soft errors have affected flip-flop implemented registers on the semiconductor chip. A signature of these flip-flop implemented registers on the semiconductor chip is periodically captured. The signature allows for the integrity of the flip-flop implemented registers to be constantly monitored. A soft error occurring on any of the flip-flop implemented registers can be immediately detected. In response to the detection, an interrupt is raised to notify software to take action.

Abstract: Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip.

Abstract: A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is finished updating the holding register and the holding register is ready to commit to the target register, a source identifier is added to a register bus. The source identifier identifies the holding register as the originator of the transaction on the register bus. The N holding registers are able to simultaneously handle N register transactions. The max value of N is 2n, where n is the number of bits in the source identifier.

Abstract: A resource requirements method and system is provided. The method includes identifying dependencies and calculating a utilization value for a source server. The source server is mapped to an application and a source infrastructure is compared to a target infrastructure. Deficiencies and differences associated with the target infrastructure are determined and dependency requirements for fulfillment in the target infrastructure are generated. The utilization value is compared to a resource capability of the target server and resource requirements for fulfillment on the target server are generated.

Abstract: Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip. Each pipe on the network chip implements a dynamic port renumbering scheme that dynamically assigns a relative port number for each port assigned to that pipe. The dynamic port renumbering scheme allows for internal parallelism without increasing the total amount of state space required for the ports on the network chip.

Abstract: Embodiments of the apparatus for forming a hash input from packet contents relate to a programmable flexible solution to form hash inputs, allowing for hardware changes and for adding support for newer protocols as and when they are defined in the future. A packet is split into individual layers. Each layer is given a unique layer type number that helps identify what that layer is. Based on the layer type, each layer is expanded to a generic format. Each layer has a set of hash commands that is generic to that layer. Fields of each hash command are fieldOffset, fieldLen, hashMask, and hashMaskMSB. These hash commands allow information in the packet to be extracted in a programmable manner. The fields extracted from each protocol layer of the packet are concatenated to form a hash layer. A bit vector indicates which hash layers are used to form the hash input.

Abstract: Embodiments of the apparatus for extracting data from packets relate to programmable layer commands that allow fields from packets to be extracted. A packet is split into individual layers. Each layer is given a unique layer type number that identifies the layer. Based on the layer type, each layer is expanded to a generic format. Each layer has a set of layer commands that is generic to that layer. Fields of each layer command are fieldOffset and fieldLen. These layer commands allow information in the packet to be extracted in a programmable manner. Extracted fields from each protocol layer are concatenated to form a token layer. All token layers are concatenated to form a final token, which is used for further processing of the packet.

Abstract: Embodiments of the apparatus for handling large protocol layers relate to an implementation that optimizes a field selection circuit. This implementation provides software like flexibility to a hardware parser engine in parsing packets. The implementation limits a size of each layer and splits any layer that exceeds that size into smaller layers. The parser engine extracts data from the split layers just as it would from a non-split layer and, then, concatenates the extracted data in a final result.

Abstract: Embodiments of the apparatus for modifying packet headers relate to a rewrite engine that represents each protocol header of packets in a generic format specific to that protocol to enable programmable modifications of packets, resulting in hardware and software flexibility in modifying packet headers. Software programs generic formats in a hardware table for various protocols. The rewrite engine is able to detect missing fields from a protocol header and is able to expand the protocol header to a maximum size such that the protocol header contains all possible fields of that protocol. Each of the fields has the same offset irrespective of which variation of the protocol the protocol header corresponds to. The expanded protocol header is represented by a data structure that is independent of a size of the protocol header.

Abstract: Embodiments of the apparatus for reducing latency in a flexible parser relate to an implementation that optimizes each parser engine within the parser. A packet enters the parser. Each of the parser engines processes the packet if processing is required. Otherwise, the parser engine simply forwards the packet through without processing the packet, thereby reducing latency. Each parser engine includes a memory. The memory stores bypass data and status information that indicates whether parsing for this packet is completed and, thus, no further processing is required by subsequent parser engines. Each parser engine also includes a counter, which is incremented whenever a packet enters the parser engine and is decremented whenever a packet exists the parser engine. A packet bypasses the parser engine based on the counter of the parser engine and the status information of that packet.

Abstract: Embodiments of the apparatus for modifying packet headers relate to a rewrite engine that represents each protocol header of packets in a generic format specific to that protocol to enable programmable modifications of packets, resulting in hardware and software flexibility in modifying packet headers. Software programs generic formats in a hardware table for various protocols. The rewrite engine is able to detect missing fields from a protocol header and is able to expand the protocol header to a maximum size such that the protocol header contains all possible fields of that protocol. Each of the fields has the same offset irrespective of which variation of the protocol the protocol header corresponds to. In a bit vector, all newly added fields are marked invalid (represented by 0), and all existing fields are marked valid (represented by 1). Software modification commands allow data to be replaced, removed and inserted.

Abstract: Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived at. The packets can be distributed for processing within the network chip.

Abstract: A resource requirements method and system is provided. The method includes identifying dependencies and calculating a utilization value for a source server. The source server is mapped to an application and a source infrastructure is compared to a target infrastructure. Deficiencies and differences associated with the target infrastructure are determined and dependency requirements for fulfillment in the target infrastructure are generated. The utilization value is compared to a resource capability of the target server and resource requirements for fulfillment on the target server are generated.

Abstract: A method, system and a computer program product for forecasting in computing environments includes capturing an architectural pattern in a first computing environment, detecting a state in the captured architectural pattern, identifying an architectural pattern identical to the captured architectural pattern in one or more other computing environments and forecasting the detected state in the one or more other computing environments.

Abstract: A resource requirements method and system is provided. The method includes identifying dependencies and calculating a utilization value for a source server. The source server is mapped to an application and a source infrastructure is compared to a target infrastructure. Deficiencies and differences associated with the target infrastructure are determined and dependency requirements for fulfillment in the target infrastructure are generated. The utilization value is compared to a resource capability of the target server and resource requirements for fulfillment on the target server are generated.

Abstract: A method includes receiving a direct current (DC) signal at an inverter control system from a bus. The inverter control system includes an inverter and an inverter controller. The received DC signal is compared to a reference value. Based at least in part on the comparison, the inverter controller determines whether to adjust a magnitude of the DC signal received through the bus. The DC signal is converted to an alternating current (AC) signal with the inverter, and the AC signal is provided to a load.

Abstract: A resource requirements method and system is provided. The method includes identifying dependencies and calculating a utilization value for a source server. The source server is mapped to an application and a source infrastructure is compared to a target infrastructure. Deficiencies and differences associated with the target infrastructure are determined and dependency requirements for fulfillment in the target infrastructure are generated. The utilization value is compared to a resource capability of the target server and resource requirements for fulfillment on the target server are generated.