Abstract: A system and method of employing a façade to intercept change action commands to be carried out on a target IT endpoint resource. The intercepted commands are compared to information on a corresponding change ticket and any differences, along with the information such as target history, are used to compute a risk assessment of the risk in allowing the intercepted change action commands to be executed. Where the risk exceeds a predetermined threshold, the intercepted change action commands may be modified or eventually aborted.

Abstract: Techniques for automatically documenting activity data in connection with execution of a ticket are provided. The techniques include receiving activity data in connection with execution of a ticket, processing the activity data to generate an output, and appending the processed activity data output to the ticket for ticket enrichment. Techniques for identifying a wrong choice of resolution code in connection with a ticket are also provided. The techniques include analyzing one or more previous tickets to determine a category in which a ticket belongs, determining whether a user-defined code is in variance with a system-suggested code, and sending an alert to a system administrator if the user-defined code is different than the system-suggested code.

Abstract: A method for managing static data traffic of at least one light path in an optical network, comprising the steps of achieving load balanced path routing for the at least one light path, assigning wavelengths to demands of the at least one light path, and, switching the at least one light path according to its assigned wavelength. A method for managing dynamic data traffic of at least one light path in an optical network, comprising the steps of routing the K-shortest path, which has the largest interference length (L), and, assigning waveband with a First-Fit network topology based on band/port number restriction and minimum weight.

Abstract: A method for managing static data traffic of at least one light path in an optical network, comprising the steps of achieving load balanced path routing for the at least one light path, assigning wavelengths to demands of the at least one light path, and, switching the at least one light path according to its assigned wavelength. A method for managing dynamic data traffic of at least one light path in an optical network, comprising the steps of routing the K-shortest path, which has the largest interference length (L), and, assigning waveband with a First-Fit network topology based on band/port number restriction and minimum weight.

Abstract: A queuing system uses a common buffer for receiving input data from multiple-inputs, by allocating memory-elements in the common buffer to each input-stream, as the streams provide their input data. To allow for an independently controlled unloading of the individual data-items from the multiple-input common buffer, the system maintains a mapping of the memory locations of the buffer that is allocated to each data-item in each input-stream. To minimize the memory and overhead associated with maintaining a mapping of each data-item, memory locations that are allocated to each input-stream are maintained in a sequential, first-in, first-out queue. When a subsequent receiving device acknowledges that it is ready to receive a data-item from a particular input-stream, the identification of the allocated memory location is removed from the input-stream's queue, and the data-item that is at the allocated memory in the common buffer is provided to the receiving device.

Abstract: In an example embodiment, an apparatus providing communication in a computer system, comprises, a plurality of modules each having a master port and a slave port A secondary bus is shared between the plurality of modules for transmitting data and address information between a master port and a slave port of two modules. A bridge circuit coupled to the plurality of modules and the secondary bus, individually grants modules of the plurality of modules, access to the secondary bus. The bridge circuit establishes point-to-point communication paths between a master port and a slave port of two modules of the plurality of modules, for communicating handshake signals between them, and controls address and data phases between modules; two address phases can be outstanding simultaneously. The bridge circuit forwards address and data phases from one module to another module of the plurality of modules; the plurality of modules only interface with the bridge circuit.

Abstract: The reliability and operability of semiconductor devices is improved using a circuit arrangement and method that improves the ability to manage data storage and retrieval. According to one example embodiment of the present invention, a memory device includes a dynamically configurable page table having a plurality of pages. The page table is dynamically configurable to at least two organizations, and each page includes a multitude of memory storage locations adapted to store data. A controller is adapted to track memory requests and to configure the page table to one of the at least two organizations during a memory refresh cycle, wherein the configuration is effected in response to the tracked memory requests. In this manner, the page table can be adapted to improve the effectiveness and speed of data storage and retrieval.

Abstract: An optimized CPU-memory high bandwidth multibus structure simultaneously supporting design reusable blocks. A system in accordance with the present invention communicatively couples the internal components (e.g., CPU, memory, etc.) and peripheral devices (e.g., display, keyboard, etc.) of a computer system by dividing the components into two logical subdivisions. One subdivision includes the memory and CPU(s) of the computer system while the other subdivision includes the remaining components. In accordance with the present invention, each subdivision of components is interconnected to the other components of its subdivision by a bus scheme. Both subdivision bus schemes are interconnected by circuitry referred to as a bridge, which enables them to intercommunicate. As such, the components connected to the separate subdivision bus schemes are able to intercommunicate.

Abstract: An interface and process for re-ordering data transactions between a master device and a target device. The present invention applies to target devices that interface to master devices such that both masters and slaves are capable of handling the re-ordering of outstanding requests. In such an interface where data transactions can be in any order, certain events may occur that force the reordering to be limited to either before or after the event. These events, also referred to as synchronizing events herein, require that transactions sampled before the event must be completed before transactions sampled after the event are completed. The present invention is capable of handling such synchronizing events while maximizing reordering to gain maximum performance benefits.

Abstract: An apparatus for and a method of arbitrating a stream of access requests over multiple outputs. In one embodiment, the apparatus is implemented with D*[W+(N+1) log.sub.2 D] storage elements, where D is a maximum number of outstanding requests allowed by an issuing agent, N is a number of different request types, and W is a width of access requests measured in bits. The present embodiment comprises a main queue, an input address selection circuit coupled to the main queue for selecting storage locations to receive a stream of access requests, and a plurality of output address selection circuits coupled to the main queue for selecting storage locations to be read. Significantly, the input address selection circuit includes an input address list pointing to vacant storage locations in the main queue, and the input address list is updated each time an access request is stored in, or read out from, the main queue.

Abstract: A method of and a system for allowing cacheable system memory to be accessed in a non-cacheable manner. In one embodiment of the present invention, a computer system is tricked during POST (Power-On Self-Test) to reserve a first region in a non-cacheable address space for a virtual peripheral device. The computer system is then tricked during operating system startup to reserve a second region in a cacheable address space. In the present embodiment, the first region is then mapped to the second region such that accesses to the first region is automatically forwarded to the second region. As a result, objectives of the present invention are achieved as cacheable memory may be accessed via accessing non-cacheable memory of the computer system.

Abstract: An apparatus for and a method of arbitrating a stream of access requests over multiple outputs. In one embodiment, the apparatus is implemented with D*[W+(N+1)log.sub.2 D] storage elements, where D is a maximum number of outstanding requests allowed by an issuing agent, N is a number of different request types, and W is a width of access requests measured in bits. The present embodiment comprises a main queue, an input address selection circuit coupled to the main queue for selecting storage locations to receive a stream of access requests, and a plurality of output address selection circuits coupled to the main queue for selecting storage locations to be read. Significantly, the input address selection circuit includes an input address list pointing to vacant storage locations in the main queue, and the input address list is updated each time an access request is stored in, or read out from, the main queue.

Abstract: A centrally controlled interface scheme for promoting design reusable circuit blocks. A system in accordance with the present invention enables existing circuit blocks of a computer system to be connected in a wide variety of shared bus standards while their internal circuitry remains unchanged. Specifically, within an embodiment of the present invention, the sharing of signals over a shared bus scheme is exclusively controlled by external bus control circuits which are controlled by an external control unit. As such, the circuit blocks are designed to operate as if they have dedicated (e.g., point-to-point) lines to the other circuit blocks with which they communicate. By implementing the circuit blocks and external control of the shared signals in this fashion, the bus interconnection scheme of the circuit blocks can be changed to fit desired performance levels or expected traffic levels, while the circuit blocks themselves remain unchanged.

Abstract: A method and system for latching an address for accessing a synchronous static random access memory (SRAM). A first address status signal of the SRAM is driven active, triggering an SRAM to latch the address on an address bus coupled therewith. A second address status signal is received when a valid address is placed on the address bus. In response, the first address status signal is driven inactive. This forces the last address latched by the SRAM to be the one indicated by the second address status signal. Then, a determination is made as to whether SRAM access is required based on the address placed on the bus. SRAM access may not be required if the current cycle is either non-cacheable or a miss in the SRAM. When SRAM access is not required, the first address status signal is driven active. In the alternative, when SRAM access is required, the first address status signal is maintained inactive. The first address status signal is maintained inactive until the SRAM is ready to accept a second address.