Capacitor with discrete dielectric material

- Micron Technology, Inc.

The invention includes methods of forming capacitors and capacitor constructions. In one implementation, a method of forming a capacitor includes forming a first capacitor electrode. A first layer of a first capacitor dielectric material is formed over the first capacitor electrode. A second layer of the first capacitor dielectric material is formed on the first layer. A second capacitor electrode is formed over the second layer of the first capacitor dielectric material. A capacitor in accordance with an implementation of the invention includes a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same capacitor dielectric material.

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Description
RELATED PARENT DATA

This application is a divisional of U.S. patent application Ser. No. 09/059,057 filed Apr. 10, 1998 now U.S. Pat. No. 6,730,559 entitled “Capacitors and Methods of Forming Capacitors”, naming Vishnu K. Agarwal and Garo J. Derderian as inventors, the disclosure of which is incorporated by reference.

TECHNICAL FIELD

This invention relates to capacitors and to methods of forming capacitors.

BACKGROUND OF THE INVENTION

Typical capacitors comprise a pair of conductive electrodes spaced apart by intervening capacitor dielectric material. As integrated circuitry becomes denser and as individual electronic components such as capacitors get smaller, integrated circuitry fabricators face the challenge of developing capacitor constructions and materials which achieve desired capacitance despite the decreasing size. Example materials under consideration for capacitor dielectric layers include titanates and tantalum pentoxide. These and other capacitor dielectric layer materials can occur in crystalline and in amorphous phases.

It is generally known that the capacitance of dielectric materials such as these can, at least initially, be increased from their as-deposited form by annealing. Such annealing can promote crystallization, re-crystallization or crystal realignment which can facilitate increase in capacitance and reduction in current leakage through the material. However, such annealing can also cause single crystals to be formed in the dielectric layer which in essence extend entirely through the dielectric layer between the layer's opposing surfaces. Annealing or crystal formation to this degree can undesirably have the effect of increasing current leakage. This is primarily due to continuous paths being provided by the continuous grain boundaries for current leakage from one side of the layer to the other. It would be desirable to improve upon these adverse characteristics of capacitor dielectric layer materials.

SUMMARY OF THE INVENTION

The invention in one aspect includes methods of forming capacitors and to capacitor constructions. In one implementation, a method of forming a capacitor includes forming a first capacitor electrode. A first layer of a first capacitor dielectric material is formed over the first capacitor electrode. A second layer of the first capacitor dielectric material is formed on the first layer. A second capacitor electrode is formed over the second layer of the first capacitor dielectric material. In accordance with another implementation, the first layer comprises a first titanate compound comprising capacitor dielectric material and the second layer comprises a different second titanate compound comprising capacitor dielectric material. A capacitor in accordance with an implementation of the invention includes a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same capacitor dielectric material. A capacitor in accordance with another implementation includes a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of two different capacitor dielectric materials, said two capacitor dielectric materials including two different titanate compounds. A capacitor in accordance with still another implementation includes a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of two different capacitor dielectric materials, one of the two different materials comprising a titanate compound and the other comprising Ta2O5.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

FIG. 1 is a diagrammatic sectional view of a wafer fragment at one processing step in accordance with the invention.

FIG. 2 is a view of the FIG. 1 wafer fragment at a step subsequent to that shown by FIG. 1.

FIG. 3 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 2.

FIG. 4 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 3.

FIG. 5 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 4.

 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).

A semiconductor wafer in process in accordance with one aspect of the invention is indicated in FIG. 1 with reference numeral 10. Such comprises a semiconductive substrate in the form of a bulk monocrystalline silicon substrate 12. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. A first capacitor electrode 16 is formed over substrate 12. Exemplary materials include conductively doped polysilicon or TiN. An exemplary thickness for layer 16 is from 100 Angstroms to 1500 Angstroms.

A first layer 18 of a first capacitor dielectric material is formed over first capacitor electrode 16. Exemplary and preferred materials include barium strontium titanate (BST), strontium titanate (ST), strontium bismuth titanate (SBT), lead lanthanate zirconia titanate (PLTZ), Ta2O5, and mixtures thereof. The preferred method of depositing layer 18 is by chemical vapor deposition. Layer 18 as initially formed can be either crystalline or amorphous, with an initial amorphous structure being preferred and shown in the fabrication of a capacitor dielectric layer in accordance with this aspect of the invention. Regardless, first layer 18 of first capacitor dielectric material is preferably subsequently annealed at a temperature of at least 300° C. for a time period sufficient to achieve a selected crystalline structure intended to densify and facilitate capacitive properties of such material (FIG. 2). Exemplary anneal conditions include a temperature range of from about 300° C. to about 1200° C. at a pressure of from about 2 mTorr to about 5 atm for a treatment time of anywhere from about 1 minute to 2 hours. Unfortunately as described above with respect to the prior art, such annealing can cause sufficient recrystallization to form singular grains at various locations throughout layer 18 having grain boundaries which extend from one surface of the layer to the other, as shown.

Referring to FIG. 3, a second layer 20 of the same first capacitor dielectric material of layer 18 is formed on first layer 18 after the preferred layer 18 annealing. Second layer 20 is also preferably chemical vapor deposited, and can initially be formed to be amorphous or crystalline. Preferably, it is initially formed to be amorphous as shown. Further, the thickness of first layer 18 of the first material is preferably chosen to be from about 10% to about 90% of the finished combined thickness of first layer 18 and second layer 20. An exemplary thickness range for the combination of layers 18 and 20 is from 60 Angstroms to 1000 Angstroms. By way of example only where the material of layers 18 and 20 comprises BST, an example thickness for each layer 18 and 20 is 150 Angstroms.

Referring to FIG. 4, a second capacitor electrode 22 is formed over: second layer 20 of the first capacitor dielectric material. An exemplary thickness range for electrode 22 is from 100 Angstroms to 2500 Angstroms. Further, diffusion barrier layers, if desired, can be positioned anywhere intermediate the composite of layers 18 and 20, and first electrode 16 and second electrode 22. Regardless, it is most preferable that second layer 20 of the first material not be exposed to a temperature of 500° C. or greater before deposition of any subsequent layer thereover. In certain instances, exposure to such temperature for a sufficient period of time could cause complete crystal realignment relative to the composite layer of layers 18 and 20, and undesirably form grain boundaries which extend from the base of layer 18 clear through to the top of layer 20.

Electrode layer 22 and/or any intervening diffusion barrier or other layer provided over layer 20 are chosen and deposited in such a way that a degree of desired stress (either tensile or compressive) will be imparted into layer 20, either during formation/deposition or subsequently such as when it is heated. Such stress can be imparted inherently by the electrode material during its deposition, or by choosing deposition/forming conditions that themselves impart a desired stress. For example, selection of temperature and pressure conditions during deposition/formation of the electrode layer can be selected to impart a desired stress regardless of the electrode material being deposited. Alternately, the material can be chosen relative to the second capacitor dielectric layer to impart a desired tensile or compressive stress. Such example materials for use with the preferred titanates and pentoxides capacitor dielectric layers include TiNX, WNX, TaNX, PtRhX, PtRuX PtIrX, and mixtures thereof. Further alternately, and by way of example only, the second capacitor electrode material could be doped with a conductivity enhancing impurity during its formation chosen to achieve a selected stress on the second layer of the capacitor dielectric layer.

Regardless, such stress can largely prevent complete recrystallization of the same material of layers 18 and 20. Exemplary dedicated anneal conditions include temperatures ranging from 500° C. to 1000° C., and pressures ranging from 50 mTorr to 50 atmospheres. Accordingly, layer 20 is preferably ultimately annealed either with a dedicated anneal step or in conjunction with other wafer processing to render it substantially crystalline in its finished composition. Regardless, the preferred capacitor construction will comprise a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers: of the same capacitor dielectric material, as shown.

Accordingly in the above described preferred embodiment, first layer 18 of the capacitor dielectric layer material is essentially provided with a selected finished crystalline structure prior to formation of second layer 20 thereon. Such is achieved by the crystallization or recrystallization anneal immediately prior to formation of layer 20. Also in the preferred embodiment, the final composition of second layer 20 of the first material is also desirably formed to be crystalline, although alternately such could remain amorphous if so initially deposited. In the preferred embodiment for a capacitor dielectric layer where both of layers 18 and 20 are crystalline in their final form, an interface line 19 essentially forms therebetween where such discrete layers contact (FIG. 5). Interface line 19 is characterized by a perceptible change in crystallinity from one layer to the other, such as shown or evidenced in this example by a substantial lateral shift or displacement in grain boundaries from one layer to the other.

In accordance with another implementation of the invention, first layer 18 can comprise a first titanate compound and second layer 20 can comprise a different second titanate compound. In accordance with still another implementation of the invention, first layer 18 can comprise one capacitor dielectric layer material and second layer 20 can comprise another different capacitor dielectric layer material, with one of the materials comprising a titanate compound and the other comprising Ta2O5. By way of example only, example titanate compounds are those referred to above.

Fluorine or other grain boundary passivation treatments can also be conducted relative to the first and second layers of material intermediate or after such layers have been deposited. Example such treatments are described in our U.S. Pat. No. 5,665,611 and references cited therein.

In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A capacitor comprising a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of the identical capacitor dielectric composition comprising a member selected from the group consisting of a strontium titanate, a strontium bismuth titanate, a lead lanthanate zirconia titanate, and mixtures thereof, both of the discrete layers being crystalline, and comprising an interface where the discrete layers contact which is characterized by a perceptible change in crystallinity from one layer to the other, the perceptible change in crystallinity being characterized by a perceptible interface line between the two discrete layers and a perceptible lateral shift in grain boundaries from the one layer to the other.

2. The capacitor of claim 1 wherein the identical capacitor dielectric composition further comprises a barium strontium titanate compound.

3. The capacitor of claim 1 wherein the identical capacitor dielectric composition further comprises Ta2O5.

4. The capacitor of claim 1 constituting an entire capacitor dielectric region between the pair of capacitor electrodes, the entire capacitor dielectric region consisting essentially of the composite of the two immediately juxtaposed and contacting, yet discrete, layers of the identical capacitor dielectric composition.

5. The capacitor of claim 2 constituting an entire capacitor dielectric region between the pair of capacitor electrodes, the entire capacitor dielectric region consisting essentially of the composite of the two immediately juxtaposed and contacting, yet discrete, layers of the identical capacitor dielectric composition.

6. The capacitor of claim 3 constituting an entire capacitor dielectric region between the pair of capacitor electrodes, the entire capacitor dielectric region consisting essentially of the composite of the two immediately juxtaposed and contacting, yet discrete, layers of the identical capacitor dielectric composition.

7. The capacitor of claim 1 wherein at least one of the electrodes predominately comprises a material selected from the group consisting of TiNX, WNX, TaNX, PtRhX, PtRuX, PtIrX, and mixtures thereof.

8. The capacitor of claim 7 constituting an entire capacitor dielectric region between the pair of capacitor electrodes, the entire capacitor dielectric region consisting essentially of the composite of the two immediately juxtaposed and contacting, yet discrete, layers of the identical capacitor dielectric composition.

9. The capacitor of claim 1 wherein one of the two layers has a thickness of from 10% to 90% of a combined thickness of the two layers.

10. The capacitor of claim 9 constituting an entire capacitor dielectric region between the pair of capacitor electrodes, the entire capacitor dielectric region consisting essentially of the composite of the two immediately juxtaposed and contacting, yet discrete, layers of the identical capacitor dielectric material.

11. The capacitor of claim 9 wherein at least one of the electrodes predominately comprises a material selected from the group consisting of TiNX, WNX, TaNX, PtRhX, PtRuX PtIrX, and mixtures thereof.

Referenced Cited
U.S. Patent Documents
3210607 October 1965 Flanagan
3691537 September 1972 Burgess et al.
3755692 August 1973 Mundy
3886415 May 1975 Genthe
4333808 June 8, 1982 Bhattacharyya et al.
4437139 March 13, 1984 Howard
4464701 August 7, 1984 Roberts et al.
4873610 October 10, 1989 Shimizu et al.
4891682 January 2, 1990 Yusa et al.
4952904 August 28, 1990 Johnson et al.
5053917 October 1, 1991 Miyasaka et al.
5079191 January 7, 1992 Shinriki et al.
5142438 August 25, 1992 Reinberg et al.
5191510 March 2, 1993 Huffman
5192871 March 9, 1993 Ramakrishnan et al.
5234556 August 10, 1993 Oishi et al.
5279985 January 18, 1994 Kamiyama
5293510 March 8, 1994 Takenaka
5316982 May 31, 1994 Taniguchi
5330935 July 19, 1994 Dobuzinsky et al.
5335138 August 2, 1994 Sandhu et al.
5348894 September 20, 1994 Gnade et al.
5352623 October 4, 1994 Kamiyama
5362632 November 8, 1994 Mathews
5372859 December 13, 1994 Thakoor
5390072 February 14, 1995 Anderson et al.
5397446 March 14, 1995 Ishihara et al.
5411912 May 2, 1995 Sakamoto
5438012 August 1, 1995 Kamiyama
5442213 August 15, 1995 Okudaira
5442585 August 15, 1995 Eguchi et al.
5452178 September 19, 1995 Emesh et al.
5466629 November 14, 1995 Mihara et al.
5468687 November 21, 1995 Carl et al.
5471364 November 28, 1995 Summerfelt et al.
5504041 April 2, 1996 Summerfelt
5508221 April 16, 1996 Kamiyama
5508953 April 16, 1996 Fukuda et al.
5510651 April 23, 1996 Maniar et al.
5552337 September 3, 1996 Kwon et al.
5555486 September 10, 1996 Kingon et al.
5557122 September 17, 1996 Shrivastava et al.
5561307 October 1, 1996 Mihara et al.
5580812 December 3, 1996 Ikemasu et al.
5585300 December 17, 1996 Summerfelt
5617290 April 1, 1997 Kulwicki et al.
5641702 June 24, 1997 Imai et al.
5654222 August 5, 1997 Sandhu et al.
5661319 August 26, 1997 Fujii et al.
5663088 September 2, 1997 Sandhu et al.
5665210 September 9, 1997 Yamazaki
5668040 September 16, 1997 Byun
5675028 October 7, 1997 Neumayer et al.
5688724 November 18, 1997 Yoon et al.
5723382 March 3, 1998 Sandhu et al.
5728603 March 17, 1998 Emesh et al.
5753547 May 19, 1998 Ying
5760474 June 2, 1998 Schuele
5780115 July 14, 1998 Park et al.
5780359 July 14, 1998 Brown et al.
5783253 July 21, 1998 Roh
5786248 July 28, 1998 Schuegraf
5790366 August 4, 1998 Desu et al.
5798903 August 25, 1998 Dhote et al.
5807774 September 15, 1998 Desu et al.
5814852 September 29, 1998 Sandhu et al.
5834060 November 10, 1998 Kawahara et al.
5834345 November 10, 1998 Shimizu
5837591 November 17, 1998 Shimada et al.
5837593 November 17, 1998 Park et al.
5838035 November 17, 1998 Ramesh
5843830 December 1, 1998 Graettinger et al.
5844771 December 1, 1998 Graettinger et al.
5858873 January 12, 1999 Vitkavage et al.
5864496 January 26, 1999 Mueller et al.
5876788 March 2, 1999 Bronner
5888295 March 30, 1999 Sandhu et al.
5899740 May 4, 1999 Kwon
5910218 June 8, 1999 Park et al.
5910880 June 8, 1999 DeBoer et al.
5913125 June 15, 1999 Brouillette et al.
5916634 June 29, 1999 Fleming et al.
5920775 July 6, 1999 Koh
5930106 July 27, 1999 Deboer et al.
5930584 July 27, 1999 Sun et al.
5933316 August 3, 1999 Ramakrishnan et al.
5943580 August 24, 1999 Ramakrishnan
5955758 September 21, 1999 Sandhu et al.
5970369 October 19, 1999 Hara et al.
5973911 October 26, 1999 Nishioka
5985714 November 16, 1999 Sandhu et al.
5990507 November 23, 1999 Mochizuki et al.
5998247 December 7, 1999 Wu
6010744 January 4, 2000 Buskirk et al.
6010931 January 4, 2000 Sun et al.
6015989 January 18, 2000 Horikawa et al.
6017789 January 25, 2000 Sandhu et al.
6027969 February 22, 2000 Huang et al.
6028359 February 22, 2000 Merchant et al.
6028360 February 22, 2000 Nakamura et al.
6037205 March 14, 2000 Huh et al.
6046469 April 4, 2000 Yamazaki et al.
6048764 April 11, 2000 Suzuki et al.
6051859 April 18, 2000 Hosotani et al.
6054730 April 25, 2000 Noguchi
6081034 June 27, 2000 Sandhu et al.
6090659 July 18, 2000 Laibowitz et al.
6093966 July 25, 2000 Venkatraman et al.
6096597 August 1, 2000 Tsu et al.
6143597 November 7, 2000 Matsuda et al.
6150208 November 21, 2000 Deboer et al.
6150706 November 21, 2000 Thakur et al.
6168985 January 2, 2001 Asano et al.
6180481 January 30, 2001 DeBoer
6197653 March 6, 2001 Khamankar
6201728 March 13, 2001 Narui et al.
6204203 March 20, 2001 Narwankar et al.
6235594 May 22, 2001 Merchant et al.
6275370 August 14, 2001 Gnade et al.
6282080 August 28, 2001 DeBoer et al.
6376332 April 23, 2002 Yanagita et al.
6727143 April 27, 2004 Hui et al.
Foreign Patent Documents
1-222469 May 1989 JP
403209869 September 1991 JP
04162527 June 1992 JP
5211288 August 1993 JP
05-221644 August 1993 JP
405211288 August 1993 JP
405243524 September 1993 JP
405343641 December 1993 JP
06-021333 January 1994 JP
406061449 March 1994 JP
7161827 June 1995 JP
WO 9744797 November 1997 WO
Other references
  • IBM Technical Disclosure Bulletin: “Process for Selective Etching of Tantalum Oxide”, vol. 27, No. 12, May 1985, one page.
  • U.S. Appl. No. 09/512,149, filed Feb. 23, 2000, Agarwal.
  • Chang et al.; “Structures of tantalum pentoxide thin films formed by reactive sputtering of Ta metal”,Elseview Science S.A. 1995, Thin Solid Films pp. 56-63.
  • Van Zant, “Microchip Fabrication: A Practical Guide to Semiconductor Processing” 4th Edition, McGraw Hill 2000, pp. 388-389.
  • H. Shinriki and M. Nakata, IEEE Transaction On Electron Devices vol. 38 No. 3 Mar. 1991.
  • U.S. Appl. No. 09/033,063, filed Feb. 28, 1998, Al-Shareef et al.
  • U.S. Appl. No. 09/033,064, filed Feb. 28, 1998, Al-Shareef et al.
  • U.S. Appl. No. 09/058,612, filed Apr. 10, 1998, Agarwal et al.
  • U.S. Appl. No. 09/083,257, filed May 21, 1998, Al-Shareef et al.
  • U.S. Appl. No. 09/137,780, filed Aug. 20, 1998, Al-Shareef et al.
  • U.S. Appl. No. 09/074,638, filed May 7, 1998, Agarwal et al.
  • U.S. Appl. No. 08/858,027, filed May 16, 1997, Sandhu et al.
  • U.S. Appl. No. 08/881,561, filed Jun. 24, 1997, Sandhu et al.
  • U.S. Appl. No. 09/086,389, filed May 28, 1998, Sandhu et al.
  • U.S. Appl. No. 09/122,473, filed Jul. 23, 1998, Schuegraf.
  • U.S. Appl. No. 09/098,035, filed Jun. 15, 1998, Deboer et al.
  • U.S. Appl. No. 09/185,412, filed Nov. 3, 1998, Graettinger et al.
  • U.S. Appl. No. 09/229,518, filed Jan. 13, 1999, DeBoer et al.
  • U.S. Appl. No. 08/994,054, filed Aug.1997, Parekh et al.
  • U.S. Appl. No. 08/670,644, Graettinger et al.
  • U.S. Appl. No. 08/542,430, Schuegraf.
  • McIntyre, Paul C. et al., Kinetics and Mechanisms of TiN Oxidation Beneath Pi.TiN Films. J. Appl. Phys., vol. 82, No. 9, pp. 4577-4585 (Nov. 1997).
  • Lesaicherre, P-Y et al., a Gbit-Scale DRAM Stacked Capacitor Technology with ECR MOCVD SrTiO3and RIE Patterned RuO2/TIN Storage Nodes, 1994 IEEE, pp. 831-834.
  • Onishi, Shigeo et al., Half-Micron Ferroelectric Memory Cell Technology With Stacked Capacitor Structure, 1994 IEEE, IDEM 94-843, pp. 843-846.
  • Kamiyama, S. et al., Ultrathin Tantalum Oxide Capacitor Dielectric Layers Fabricated Using Rapid Thermal Nitrodation Prior to Low Pressure Chemical Vapor Deposition, J. Electrochem. Soc., vol. 140, No. 6, Jun. 1993, pp. 1617-1625.
  • Eimori, T. et al., A Newly Designed Planar Stacked Capacitor Cell with High Dielectric Constant Film for 256Mbit Dram, 1993 IEEE, pp. 631-634.
  • Yamaguchi, H. et al., Structural and Electrical Characterization of SrTiO3 Thin Films Prepared by Metal Organic Chemical Vapor Deposition, Jpn. J. appl. Phys., vol. 32, 1993, Pt. 1, No. 9B, pp. 4069-4073.
  • Fazan, P.C. et al., A High-C Capacitor (20.4ƒF/μm2) with Ultrathin CVD-Ta2O5Films Deposited on Rugged Poly-Si for High Density DRAMs, 1992 IEEE, pp. 263-266.
  • Kamiyama, S., et. al., Highly Reliable 2.5μm Ta2O5Capacitor Process Technology for 256Mbit DRAMs, 1991 IEEE, pp. 827-830.
  • Farooq, M.A. et al., Tantalum nitride as a dissusion barrier between Pd2Si, CoSi2 and aluminum, 1989 American Institute of Physics, pp. 3017-3022.
  • S. Wolf and R.N. Tauber. Silicon Processing for the VLSI Era, vol. 2, Lattice Press. pages 589-591.
  • Anonymous Research Disclosure, 1989R D-0299041 titled Double High Dielectric Capacitor, Derewent-Week 198917 (Derwent World Patent Index).
Patent History
Patent number: 6891217
Type: Grant
Filed: Oct 26, 1999
Date of Patent: May 10, 2005
Assignee: Micron Technology, Inc. (Boise, ID)
Inventors: Vishnu K. Agarwal (Boise, ID), Garo J. Derderian (Boise, ID)
Primary Examiner: Amir Zarabian
Assistant Examiner: Kiesha Rose
Attorney: Wells St. John P.S.
Application Number: 09/428,125