Patents by Inventor Walter Rieger

Walter Rieger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10693000
    Abstract: A semiconductor device includes a plurality of first field-effect structures each including a polysilicon gate arranged on and in contact with a first gate dielectric, and a plurality of second field-effect structures each including a metal gate arranged on and in contact with a second gate dielectric. The plurality of first field-effect structures and the plurality of second field-effect structures form part of a power semiconductor device.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 23, 2020
    Assignee: Infineon Technologies Austria AG
    Inventor: Walter Rieger
  • Patent number: 10438945
    Abstract: A method of manufacturing a semiconductor die includes: forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain; monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver; and electrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
  • Patent number: 10283634
    Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 7, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger
  • Patent number: 9978862
    Abstract: A semiconductor die includes a semiconductor substrate having a first region and a second region isolated from the first region. A power transistor disposed in the first region of the semiconductor substrate has a gate, a source and a drain. A gate driver transistor disposed in the second region of the semiconductor substrate has a gate, a source and a drain. The gate driver transistor is electrically connected to the gate of the power transistor and operable to turn the power transistor off or on responsive to an externally-generated control signal applied to the gate of the gate driver transistor. A first contact pad is electrically connected to the source of the power transistor, and a second contact pad is electrically connected to the drain of the power transistor. A third contact pad is electrically connected to the gate of the gate driver transistor for receiving the externally-generated control signal.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
  • Publication number: 20180047719
    Abstract: A method of manufacturing a semiconductor die includes: forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain; monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver; and electrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device.
    Type: Application
    Filed: September 19, 2017
    Publication date: February 15, 2018
    Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
  • Publication number: 20170373180
    Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.
    Type: Application
    Filed: September 7, 2017
    Publication date: December 28, 2017
    Applicant: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger
  • Patent number: 9799643
    Abstract: A semiconductor die includes a III-nitride semiconductor substrate, a power HEMT (high-electron-mobility transistor) disposed in the III-nitride semiconductor substrate, and a first gate driver HEMT monolithically integrated with the power HEMT in the III-nitride semiconductor substrate. The power HEMT and the first gate driver HEMT each have a gate, a source and a drain. The first gate driver HEMT logically forms part of a driver, and is electrically connected to the gate of the power HEMT. The first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device. Additional embodiments of semiconductor dies and methods of manufacturing are also described.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Vielemeyer, Walter Rieger, Martin PöIzl, Gerhard Nöbauer
  • Publication number: 20170301784
    Abstract: A semiconductor device includes a plurality of first field-effect structures each including a polysilicon gate arranged on and in contact with a first gate dielectric, and a plurality of second field-effect structures each including a metal gate arranged on and in contact with a second gate dielectric. The plurality of first field-effect structures and the plurality of second field-effect structures form part of a power semiconductor device.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 19, 2017
    Inventor: Walter Rieger
  • Patent number: 9793391
    Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: October 17, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger
  • Patent number: 9773706
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first field-effect structure integrated in the semiconductor substrate and at least a second field-effect structure integrated in the semiconductor substrate. The first field-effect structure includes a first gate electrode comprised of a polycrystalline semiconductor material. The second field-effect structure includes a second gate electrode comprised of one of a metal, a metal alloy, a metal layer stack, a metal alloy layer stack and any combination thereof.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: September 26, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Walter Rieger
  • Patent number: 9754859
    Abstract: A semiconductor device includes a semiconductor substrate, a doped zone, a polysilicon layer and an elongate plug structure. The doped zone is within the semiconductor substrate. The polysilicon layer is disposed in a trench electrically isolated from the semiconductor substrate by an insulating layer. The elongate plug structure extends in a lateral direction in or above the semiconductor substrate. The elongate plug structure provides electrical connection between the doped zone and the polysilicon layer.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: September 5, 2017
    Assignee: Infineon Technologies AG
    Inventors: Walter Rieger, Franz Hirler, Martin Poelzl, Manfred Kotek
  • Patent number: 9646855
    Abstract: Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1?0, y1?0, z1?0) is formed. A second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2?0, z2?0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Walter Rieger, Christoph Kadow, Markus Zundel
  • Patent number: 9509284
    Abstract: An electronic circuit includes a transistor arrangement with a plurality of transistor devices, each including a control node and a load path between a first load node and a second load node, and having the load paths connected in parallel. The electronic circuit further includes a drive circuit coupled to the control node of each of the plurality of transistor devices, and configured to receive an input signal. Each of the plurality of transistor devices includes a two-dimensional electron gas (2DEG) in the load path, and a field plate adjacent the 2DEG. The drive circuit is configured to receive a load signal that represents at least one load parameter of the transistor arrangement and is configured to one of activate and deactivate at least one of the plurality of transistor devices based on the load signal.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: November 29, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Walter Rieger
  • Patent number: 9431392
    Abstract: A transistor device includes at least one first type transistor cell including a drift region, a source region, a body region arranged between the source region and the drift region, a drain region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. A gate terminal is coupled to the gate electrode, a source terminal is coupled to the source region, and a control terminal is configured to receive a control signal. A variable resistor is connected between the field electrode and the gate terminal or the source terminal. The variable resistor includes a variable resistance configured to be adjusted by the control signal received at the control terminal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 30, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Walter Rieger, Hans Weber, Michael Treu, Gerhard Nöbauer, Martin Pölzl, Martin Vielemeyer, Franz Hirler
  • Publication number: 20160233331
    Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.
    Type: Application
    Filed: November 9, 2015
    Publication date: August 11, 2016
    Applicant: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger
  • Patent number: 9406673
    Abstract: One aspect relates to a semiconductor component with a semiconductor body, a first main contact pad, a second main contact pad, a normally-on first transistor monolithically integrated in the semiconductor body and a normally-off second transistor monolithically integrated in the semiconductor body. The first transistor is a high electron mobility transistor having a first gate electrode and a first load path controllable via a first gate electrode, and the second transistor has a second gate electrode and a second load path controllable via the second gate electrode. The first load path and the second load path are electrically connected in series between the first main contact pad and the second main contact pad.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 2, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen, Walter Rieger, Anthony Sanders
  • Patent number: 9373700
    Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: June 21, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
  • Publication number: 20160043000
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first field-effect structure integrated in the semiconductor substrate and at least a second field-effect structure integrated in the semiconductor substrate. The first field-effect structure includes a first gate electrode comprised of a polycrystalline semiconductor material. The second field-effect structure includes a second gate electrode comprised of one of a metal, a metal alloy, a metal layer stack, a metal alloy layer stack and any combination thereof.
    Type: Application
    Filed: August 4, 2015
    Publication date: February 11, 2016
    Inventor: Walter Rieger
  • Publication number: 20160035862
    Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.
    Type: Application
    Filed: October 14, 2015
    Publication date: February 4, 2016
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
  • Patent number: 9202909
    Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: December 1, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger