Patents by Inventor Walter Rieger
Walter Rieger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110272761Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.Type: ApplicationFiled: July 15, 2011Publication date: November 10, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger
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Patent number: 8044459Abstract: In one embodiment, a field effect transistor has a semiconductor body, a drift region of a first conductivity type and a gate electrode. At least one trench extends into the drift region. A field plate is arranged at least in a portion of the at least one trench. A dielectric material at least partially surrounds both the gate electrode and the field plate. The field plate includes a first semiconducting material.Type: GrantFiled: November 10, 2008Date of Patent: October 25, 2011Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Walter Rieger, Andrew Wood, Mathias Born, Ralf Siemieniec, Jan Ropohl, Martin Poelzl, Oliver Blank, Uli Hiller, Oliver Haeberlen, Rudolf Zelsacher, Maximilian Roesch, Joachim Krumrey
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Publication number: 20110241170Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.Type: ApplicationFiled: April 7, 2011Publication date: October 6, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Joachim Krumrey, Sonja Krumrey
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Patent number: 8022474Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.Type: GrantFiled: September 30, 2008Date of Patent: September 20, 2011Assignee: Infineon Technologies Austria AGInventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger
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Publication number: 20110210377Abstract: A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer.Type: ApplicationFiled: February 26, 2010Publication date: September 1, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger
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Patent number: 7999287Abstract: In one embodiment a lateral HEMT has a first layer, the first layer including a semiconducting material, and a second layer, the second layer including a semiconducting material and being at least partially arranged on the first layer. The lateral HEMT further has a passivation layer and a drift region, the drift region including a lateral width wd. The lateral HEMT further has at least one field plate, the at least one field plate being arranged at least partially on the passivation layer in a region of the drift region and including a lateral width wf, wherein wf<wd.Type: GrantFiled: October 26, 2009Date of Patent: August 16, 2011Assignee: Infineon Technologies Austria AGInventors: Markus Zundel, Franz Hirler, Walter Rieger
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Publication number: 20110147796Abstract: Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1?0, y1?0, z1?0) is formed. A second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2?0, z2?0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer.Type: ApplicationFiled: December 17, 2009Publication date: June 23, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger, Christoph Kadow, Markus Zundel
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Patent number: 7943955Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.Type: GrantFiled: January 27, 2009Date of Patent: May 17, 2011Assignee: Infineon Technologies Austria AGInventors: Oliver Haeberlen, Walter Rieger, Lutz Goergens, Martin Poelzl, Johannes Schoiswohl, Joachim Krumrey
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Publication number: 20110095362Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.Type: ApplicationFiled: January 4, 2011Publication date: April 28, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
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Publication number: 20110095336Abstract: In one embodiment a lateral HEMT has a first layer, the first layer including a semiconducting material, and a second layer, the second layer including a semiconducting material and being at least partially arranged on the first layer. The lateral HEMT further has a passivation layer and a drift region, the drift region including a lateral width wd. The lateral HEMT further has at least one field plate, the at least one field plate being arranged at least partially on the passivation layer in a region of the drift region and including a lateral width wf, wherein wf<wd.Type: ApplicationFiled: October 26, 2009Publication date: April 28, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Markus Zundel, Franz Hirler, Walter Rieger
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Patent number: 7893486Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.Type: GrantFiled: January 7, 2009Date of Patent: February 22, 2011Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
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Patent number: 7875951Abstract: A semiconductor with active component and method for manufacture. One embodiment provides a semiconductor component arrangement having an active semiconductor component and a semiconductor body having a first semiconductor zone, a third semiconductor zone, and also a drift zone arranged between the first semiconductor zone and the third semiconductor zone. A patterned fourth semiconductor zone doped complementarily to the drift zone is arranged in the drift zone. A potential control structure is provided, which is connected to the patterned fourth semiconductor zone. The potential control structure is designed to connect the patterned fourth semiconductor zone, in the off state of the semiconductor component, to an electrical potential lying between the electrical potential of the first semiconductor zone and the electrical potential of the third semiconductor zone.Type: GrantFiled: December 12, 2007Date of Patent: January 25, 2011Assignee: Infineon Technologies Austria AGInventors: Walter Rieger, Franz Hirler
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Patent number: 7851349Abstract: A method for producing a connection electrode for a first semiconductor zone and a second semiconductor zone includes producing a trench extending through the first semiconductor zone right into the second semiconductor zone in such a way that the first semiconductor zone is uncovered at sidewalls of the trench and the second semiconductor zone is uncovered at least at a bottom of the trench. The method also includes applying a protective layer to a first one of the first and second semiconductor zones in the trench, and producing a first connection zone in the second of the two semiconductor zones, which is not covered by the protective layer. The method further includes depositing an electrode layer at least onto the sidewalls and the bottom of the trench for the purpose of producing the connection electrode.Type: GrantFiled: September 26, 2006Date of Patent: December 14, 2010Assignee: Infineon Technologies Austria AGInventors: Walter Rieger, Paul Ganitzer, Oliver Haeberlen, Franz Hirler, Markus Zundel, Rudolf Zelsacher, Erwin Bacher
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Patent number: 7833862Abstract: A semiconductor device and method. One embodiments provides a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material, a field electrode formed in lower portion of the trench, a cover comprising a second material above the field electrode, the second material being selectively etchable to the first isolating material, a gate dielectric on the sidewall in an upper portion of the trench and a gate electrode in the upper portion of the trench.Type: GrantFiled: March 3, 2008Date of Patent: November 16, 2010Assignee: Infineon Technologies Austria AGInventors: Oliver Blank, Uli Hiller, Maximilian Roesch, Walter Rieger
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Publication number: 20100270612Abstract: A method for producing a vertical transistor component includes providing a semiconductor substrate, applying an auxiliary layer to the semiconductor substrate, and patterning the auxiliary layer for the purpose of producing at least one trench which extends as far as the semiconductor substrate and which has opposite sidewalls. The method further includes producing a monocrystalline semiconductor layer on at least one of the sidewalls of the trench, producing an electrode insulated from the monocrystalline semiconductor layer on the at least one sidewall of the trench and the semiconductor substrate.Type: ApplicationFiled: July 11, 2010Publication date: October 28, 2010Applicant: INFINEON TECHNOLOGIES AGInventors: Martin Poelzl, Walter Rieger
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Publication number: 20100264462Abstract: A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer.Type: ApplicationFiled: April 21, 2010Publication date: October 21, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Franz Hirler, Walter Rieger, Markus Zundel
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Patent number: 7767527Abstract: A method for producing a vertical transistor component includes steps of providing a semiconductor substrate, applying an auxiliary layer to the semiconductor substrate, and patterning the auxiliary layer for the purpose of producing at least one trench which extends as far as the semiconductor substrate and which has opposite sidewalls. The method further includes producing a monocrystalline semiconductor layer on at least one of the sidewalls of the trench, producing an electrode insulated from the monocrystalline semiconductor layer on the at least one sidewall of the trench and the semiconductor substrate.Type: GrantFiled: September 30, 2005Date of Patent: August 3, 2010Assignee: Infineon Technologies AGInventors: Martin Poelzl, Walter Rieger
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Publication number: 20100187605Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.Type: ApplicationFiled: January 27, 2009Publication date: July 29, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger, Lutz Goergens, Martin Poelzl, Johannes Schoiswohl, Joachim Krumrey
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Publication number: 20100117144Abstract: In one embodiment, a field effect transistor has a semiconductor body, a drift region of a first conductivity type and a gate electrode. At least one trench extends into the drift region. A field plate is arranged at least in a portion of the at least one trench. A dielectric material at least partially surrounds both the gate electrode and the field plate. The field plate includes a first semiconducting material.Type: ApplicationFiled: November 10, 2008Publication date: May 13, 2010Applicant: Infineon Technologies Austria AGInventors: Franz Hirler, Walter Rieger, Andrew Wood, Mathias Born, Ralf Siemieniec, Jan Ropohl, Martin Poelzl, Oliver Blank, Uli Hiller, Oliver Haeberlen, Rudolf Zelsacher, Maximilian Roesch, Joachim Krumrey
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Publication number: 20100078707Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger