Abstract: A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench.

Abstract: A semiconductor device and method. One embodiments provides a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material, a field electrode formed in lower portion of the trench, a cover comprising a second material above the field electrode, the second material being selectively etchable to the first isolating material, a gate dielectric on the sidewall in an upper portion of the trench and a gate electrode in the upper portion of the trench.

Abstract: A semiconductor with active component and method for manufacture. One embodiment provides a semiconductor component arrangement having an active semiconductor component and a semiconductor body having a first semiconductor zone, a third semiconductor zone, and also a drift zone arranged between the first semiconductor zone and the third semiconductor zone. A patterned fourth semiconductor zone doped complementarily to the drift zone is arranged in the drift zone. A potential control structure is provided, which is connected to the patterned fourth semiconductor zone. The potential control structure is designed to connect the patterned fourth semiconductor zone, in the off state of the semiconductor component, to an electrical potential lying between the electrical potential of the first semiconductor zone and the electrical potential of the third semiconductor zone.

Abstract: A semiconductor structure is formed comprising a plurality of columns doped with alternating dopants. The columns are separated by trenches, and the dopant is diffused in the doped columns. The trenches are filled with semiconductor material. Other embodiments may be described and claimed.

Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.

Abstract: A trench transistor structure having a field electrode arrangement formed in trenches is disclosed. In one embodiment, the field electrode arrangement is conductively connected to subvoltage taps of a voltage divider for the purpose of stabilizing the potentials on a longer time scale than dynamic charge reversal processes.

Abstract: An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure.

Abstract: A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate.

Abstract: A semiconductor component comprises a semiconductor body comprising a first component electrode arranged on one of the surfaces of the semiconductor body, a second component electrode arranged on one of the surfaces of the semiconductor body, and a component control electrode arranged on one of the surfaces of the semiconductor body. In this case, active semiconductor element cells are arranged in a first active cell array of the semiconductor body, the semiconductor element cells comprising a first cell electrode, a second cell electrode and a cell control electrode and also a drift path between the cell electrodes. At least the component control electrode is arranged on a partial region of the semiconductor body and a second active cell array is additionally situated in the partial region of the semiconductor body below the component control electrode.

Abstract: A semiconductor structure comprises a plurality of columns doped with alternating dopants. The columns are separated by trenches, and the dopant is diffused in the doped columns. The trenches are filled with semiconductor material. Other embodiments may be described and claimed.

Abstract: A method for producing an integrated circuit is disclosed. One embodiment includes application of a barrier layer on the surface of the semiconductor body and in the trench, which barrier layer completely fills the trench and is at least partly deposited by using a CVD method. A metallization layer is produced onto a surface of the barrier layer that arose as a result of the application above the trench and the surface of the semiconductor body.

Abstract: A method for processing a semiconductor substrate less than 200 ?m thick has been provided. The substrate has one or a plurality of semiconductor elements, which may be identical or different. The substrate is arranged onto a chuck during processing, the front side of the substrate facing the chuck. During processing, an electrically conductive film, for example, made of metal, may be applied on the rear side of the substrate. The film may serve as electrical contact, heat sink or mechanical stabilizer.

Abstract: In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array (3) with cell array trenches (5) each containing a field electrode structure (11) and a gate electrode structure (10). The field electrode structure (11) is electrically conductively connected to the source metallization (15) by a connection trench (6) in the cell array (3).

Abstract: A field plate trench transistor having a semiconductor body is disclosed. In one embodiment, the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.

Abstract: Method for producing a connection electrode for two semiconductor zones arranged one above another The invention relates to a method for producing a connection electrode for a first semiconductor zone and a second semiconductor zone, which are arranged one above another and are doped complementarily with respect to one another, which method comprises the method steps of: producing a trench extending through the first semiconductor zone right into the second semiconductor zone in such a way that the first semiconductor zone is uncovered at sidewalls of the trench and the second semiconductor zone is uncovered at least at a bottom of the trench, applying a protective layer to one of the first and second semiconductor zones in the trench, producing a first connection zone in the other of the two semiconductor zones, which is not covered by the protective layer, by introducing dopant atoms into this other semiconductor zone via the trench, the connection zone being of the same conductivity type as said other semi

Abstract: A trench transistor structure having a field electrode arrangement formed in trenches is disclosed. In one embodiment, the field electrode arrangement is conductively connected to subvoltage taps of a voltage divider for the purpose of stabilizing the potentials on a longer time scale than dynamic charge reversal processes.

Abstract: When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode structure (11) in the cell array trenches (5) and the connecting trenches (6) and is etched back as far as the top edge in the connecting trenches (6), which removes it from the cell array trenches (5). The auxiliary layer (24) allows the gate oxide (20) to be patterned without a complex mask process. An edge trench (7), with an electrode, on the potential of the field electrode structure (11) shields the cell array (3) from a drain potential.

Abstract: The power transistor has a trench cell in a semiconductor body. A lower edge of the gate electrode has a profile which is not horizontal, i.e., not planar with respect to the field electrode.

Abstract: The invention relates to a method for producing a vertical transistor component, having the following method steps of: Providing a semiconductor substrate (100), applying an auxiliary layer (110) to the semiconductor substrate (100), patterning the auxiliary layer (110) for the purpose of producing at least one trench (114) which extends as far as the semiconductor substrate (100) and which has opposite sidewalls (115), producing a monocrystalline semiconductor layer (132) on at least one of the sidewalls (115) of the trench (114), producing an electrode (140) insulated from the monocrystalline semiconductor layer (132) on the at least one sidewall (115) of the trench (114) and the semiconductor substrate (100).

Abstract: A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in each case provided in the semiconductor substrate. According to the invention, the source zone and/or the channel zone are formed at the earliest after the introduction of the trenches into the semiconductor substrate by implantation and diffusion.