Abstract: A method for processing a semiconductor substrate less than 200 ?m thick has been provided. The substrate has one or a plurality of semiconductor elements, which may be identical or different. The substrate is arranged onto a chuck during processing, the front side of the substrate facing the chuck. During processing, an electrically conductive film, for example, made of metal, may be applied on the rear side of the substrate. The film may serve as electrical contact, heat sink or mechanical stabilizer.

Abstract: The present invention relates to a semiconductor arrangement with a MOS transistor which has a gate electrode (40), arranged in a trench running in the vertical direction of a semiconductor body (100), and a Schottky diode which is connected in parallel with a drain-source path (D-S) and is formed by a Schottky contact between a source electrode and the semiconductor body.

Abstract: A semiconductor device has elongate plug structures extending in the lateral direction. The plug structures serve as electrical lines in order to enable locally defined lateral current flows within the cell array, within edge regions or logic regions of the semiconductor device.

Abstract: A method for fabricating a field-effect-controllable semiconductor component includes providing a configuration having a semiconductor body with a front side, a rear side, a first terminal zone of a first conduction type, a channel zone of a second conduction type formed above the first terminal zone, and at least one control electrode adjacent the channel zone. The control electrode is insulated from the semiconductor body. A second terminal zone of the first conduction type is fabricated in the channel zone near the front side of the semiconductor body by: doping the channel zone near the front side with a first dopant concentration to fabricate a first zone of the first conduction type, and doping a section of the first zone with a second dopant concentration higher than the first dopant concentration to form a second zone of the first conduction type.

Abstract: In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array (3) with cell array trenches (5) each containing a field electrode structure (11) and a gate electrode structure (10). The field electrode structure (11) is electrically conductively connected to the source metallization (15) by a connection trench (6) in the cell array (3).

Abstract: When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode structure (11) in the cell array trenches (5) and the connecting trenches (6) and is etched back as far as the top edge in the connecting trenches (6), which removes it from the cell array trenches (5). The auxiliary layer (24) allows the gate oxide (20) to be patterned without a complex mask process. An edge trench (7), with an electrode, on the potential of the field electrode structure (11) shields the cell array (3) from a drain potential.

Abstract: Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inactive edge region of the transistor configuration and an electrically conductive connection between the electrode structures and corresponding metallizations are provided in the edge region.

Abstract: A circuit configuration for the switch-on/off control of a DMOS power transistor has at least one first gate electrode and, separate from the latter, a second gate electrode, which are capacitively coupled to one another by a capacitance distributed over the field-effect transistor and which can be driven via separate external gate electrode terminals. The circuit configuration has two individual driver circuits and a generating circuit in order to feed a first drive signal to the first gate electrode and a second drive signal to the second gate electrode, the second drive signal being delayed with respect to the first drive signal.

Abstract: A semiconductor component has a cell array formed in a semiconductor body with a number of identical transistor cells and at least one edge cell formed at an edge of the cell array. Each of the transistor cells has a control electrode, which is formed in a trench, and the edge cell has a field plate, which is formed in a trench, with a distance between the trench of the edge cell and the trench of the immediately adjacent transistor cell being less than the distance between a trench of a transistor cell and the trench of an immediately adjacent transistor cell in the cell array.

Abstract: The power transistor has a trench cell in a semiconductor body. A lower edge of the gate electrode has a profile which is not horizontal, i.e., not planar with respect to the field electrode.

Abstract: A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in each case provided in the semiconductor substrate. According to the invention, the source zone and/or the channel zone are formed at the earliest after the introduction of the trenches into the semiconductor substrate by implantation and diffusion.

Abstract: The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.

Abstract: Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inactive edge region of the transistor configuration and an electrically conductive connection between the electrode structures and corresponding metallizations are provided in the edge region.

Abstract: A semiconductor component has a cell array formed in a semiconductor body with a number of identical transistor cells and at least one edge cell formed at an edge of the cell array. Each of the transistor cells has a control electrode, which is formed in a trench, and the edge cell has a field plate, which is formed in a trench, with a distance between the trench of the edge cell and the trench of the immediately adjacent transistor cell being less than the distance between a trench of a transistor cell and the trench of an immediately adjacent transistor cell in the cell array.

Abstract: A method for fabricating a field-effect-controllable semiconductor component includes providing a configuration having a semiconductor body with a front side, a rear side, a first terminal zone of a first conduction type, a channel zone of a second conduction type formed above the first terminal zone, and at least one control electrode adjacent the channel zone. The control electrode is insulated from the semiconductor body. A second terminal zone of the first conduction type is fabricated in the channel zone near the front side of the semiconductor body by: doping the channel zone near the front side with a first dopant concentration to fabricate a first zone of the first conduction type, and doping a section of the first zone with a second dopant concentration higher than the first dopant concentration to form a second zone of the first conduction type.

Abstract: The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.

Abstract: A circuit configuration for the switch-on/off control of a DMOS power transistor has at least one first gate electrode and, separate from the latter, a second gate electrode, which are capacitively coupled to one another by a capacitance distributed over the field-effect transistor and which can be driven via separate external gate electrode terminals. The circuit configuration has two individual driver circuits and a generating circuit in order to feed a first drive signal to the first gate electrode and a second drive signal to the second gate electrode, the second drive signal being delayed with respect to the first drive signal.

Abstract: The present invention relates to a semiconductor arrangement with a MOS transistor which has a gate electrode (40), arranged in a trench running in the vertical direction of a semiconductor body (100), and a Schottky diode which is connected in parallel with a drain-source path (D-S) and is formed by a Schottky contact between a source electrode and the semiconductor body.

Abstract: A transfer system has at least one transfer device which is driven by several mutually independent drives in the direction of at least a closing/opening axis. In the event of a failure of a drive, an immediate stoppage of parts of the transfer device is prevented by coupling the drives with one another by a coupling device. This coupling device has an operating range of a low torque transmission which is normally taken up and is left only if one of the drives no longer supplies a sufficient driving power.

Abstract: An arrangement is used for transferring workpieces through a succession of machining stations of a press, a simulator or similar machining system or tool setting system. This arrangement has two spaced transport rails which are arranged parallel to one another and which can be moved by motors horizontally in a longitudinal direction thereof, vertically up and down and horizontally toward one another. Each individual transport rail is pivotally connected for a horizontal movement in each case by way of a coupling rod. Traverses are operatively connected by way of at least one of the coupling rods with one respective transport rail. The traverses can be moved by an additional transverse drive which is synchronously driven by the driving motors arranged in a closing box of the press for the horizontal movement of the transport rails toward one another.