Abstract: Atomic layer deposition methods for coating an optical substrate with magnesium fluoride. The methods include two primary processes. The first process includes the formation of a magnesium oxide layer over a surface of a substrate. The second process includes converting the magnesium oxide layer to a magnesium fluoride layer. These two primary processes may be repeated a plurality of times to create multiple magnesium fluoride layers that make up a magnesium fluoride film. The magnesium fluoride film may serve as an antireflective coating layer for an optical substrate, such as an optical lens.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.

Abstract: An electronic device may include a lenticular display. The lenticular display may have a lenticular lens film formed over an array of pixels. A plurality of lenticular lenses may extend across the length of the display. The lenticular lenses may be configured to enable stereoscopic viewing of the display such that a viewer perceives three-dimensional images. The display may have a number of independently controllable viewing zones. The viewer may be particularly susceptible to artifacts caused by crosstalk at the edge viewing zones within the primary field of view of the display. Certain types of content may also be more vulnerable to crosstalk than other types of content. Therefore, to mitigate crosstalk artifacts, the pixel value for each pixel may be adjusted based on the viewing zone of the respective pixel and content information (such as texture information or brightness information) associated with the respective pixel.

Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

Abstract: A DFOS system and machine learning method that automatically localizes manholes, which forms a key step in a fiber optic cable mapping process. Our system and method utilize weakly supervised learning techniques to predict manhole locations based on ambient data captured along the fiber optic cable route. To improve any non-informative ambient data, we employ data selection and label assignment strategies and verify their effectiveness extensively in a variety of settings, including data efficiency and generalizability to different fiber optic cable routes. We describe post-processing steps that bridge the gap between classification and localization and combining results from multiple predictions.

Abstract: A conjugate compounds or pharmaceutically acceptable salt thereof, comprises a payload and two or more kinds of cell-interacting molecules. The cell-interacting molecules are ligands capable of specifically binding to a cell surface receptor. A method of treating diseases, comprises delivering a payload to a subject.

Abstract: One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

Abstract: A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells. The logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.

Abstract: A memory circuit includes a first memory cell on a first layer, a second memory cell on a second layer different from the first layer, a first select transistor on a third layer different from the first layer and the second layer, and a first bit line extending in a first direction, and being coupled to the first memory cell and the second memory cell. The memory circuit further includes a first source line extending in the first direction, being coupled to the first memory cell, the second memory cell and the first select transistor, and being separated from the first bit line in a second direction different from the first direction. memory circuit includes a second source line extending in the first direction, and being coupled to the first select transistor.

Abstract: A wireless power transmitter can include a wireless power transfer coil designed to magnetically couple with a corresponding coil in a wireless power receiver to facilitate wireless power transfer from the wireless power transmitter to the wireless power receiver, a power converter configured to drive the wireless power transfer coil, and control and communications circuitry coupled to the wireless power transfer coil and the power converter. The control and communications circuitry can be configured to operate the power converter to drive the wireless power transfer coil so as to transfer power to the wireless power receiver in accordance with a negotiated power transfer. Simultaneously during power transfer, the control and communications circuitry can send a polling signal to detect a foreign object including a wireless transponder and reduce or stop wireless power transfer upon receiving a response to the polling signal from a foreign object including a wireless transponder.

Abstract: A high-throughput automated preprocessing method and a system are applied to a nucleic acid preprocessing apparatus including a control system, a sample transfer area, a nucleic acid extraction area, and a reagent setup area. The control system includes a user interface and guides a user to set up on the user interface. In the sample transfer area, the method includes steps of: a user selecting a sampling tube type, a test protocol and an extraction protocol on the user interface, and the control system performing a sample transfer task. In the nucleic acid extraction area, the method includes steps of: the control system performing a nucleic acid extraction task based on the selected extraction protocol. In the reagent setup area, the method includes steps of: the control system performing a reagent deployment task based on the selected test protocol, and the control system performing a nucleic acid transfer task.

Abstract: A method (of writing to a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes: setting the second bit to a logical 1 value, the setting a second bit including applying a gate voltage to the gate terminal, and applying a first source/drain voltage to the second S/D terminal; and wherein the first source/drain voltage is lower than the gate voltage.

Abstract: A method for producing polyamide particles may include: mixing a mixture comprising a polyamide, a carrier fluid that is immiscible with the polyamide, and nanoparticles at a temperature greater than a melting point or softening temperature of the polyamide and at a shear rate sufficiently high to disperse the polyamide in the carrier fluid; cooling the mixture to below the melting point or softening temperature of the polyamide to form solidified particles comprising polyamide particles having a circularity of 0.90 or greater and that comprise the polyamide and the nanoparticles associated with an outer surface of the polyamide particles; and separating the solidified particles from the carrier fluid.

Abstract: In various embodiments, optical repositioners and/or angled dispersive elements are utilized to manipulate portions of an input laser beam emitted by a group of laser emitters in order to form a multi-wavelength output beam having a high beam quality factor.

Abstract: A memory device includes a programming transistor and a reading transistor of an anti-fuse memory cell. The programming transistor includes first semiconductor nanostructures vertically spaced apart from one another, each of the first semiconductor nanostructures having a first width along a first lateral direction. The reading transistor includes second semiconductor nanostructures vertically spaced apart from one another, each of the second semiconductor nanostructures having a second width different from the first width along the second direction. The memory device also includes a first and a second gate metals. The first gate metal wraps around each of the first semiconductor nanostructures with a first gate dielectric disposed therein. The second gate metal wraps around each of the second semiconductor nanostructures with a second gate dielectric disposed therein.

Abstract: Container data sharing is provided. A second container of a cluster of containers is started to process a service request in response to detecting a failure of a first container processing the service request. The service request and data generated by the first container that failed stored on a physical external memory device is accessed. The service request and the data generated by the first container that failed is loaded on the second container from the physical external memory device via a dedicated hardware link for high-speed container failure recovery.

Abstract: The present invention relates to a hexatoxin peptide variant comprising a. an amino acid sequence which is at least 90% identical to any one of SEQ ID NOs: 27 to 29, wherein the amino acid sequence has at least one amino acid variant on position N27; b. an amino acid sequence which is at least 90% identical to any one of SEQ ID NOs: 2, 6, 7, 30 or 32, wherein the amino acid sequence has at least one amino acid variant on position N28; c. an amino acid sequence which is at least 90% identical to any one of SEQ ID NOs: 1, 3, 4, 5, 8 to 24 or 31, wherein the amino acid sequence has at least one amino acid variant on position N29; d. an amino acid sequence which is at least 90% identical to SEQ ID NO: 25, wherein the amino acid sequence has at least one amino acid variant on position N30; e. an amino acid sequence which is at least 90% identical to SEQ ID NOs: 26, wherein the amino acid sequence has at least one amino acid variant on position N31; or f.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.