Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Abstract: An aspect includes a method for dynamic random access memory (DRAM) scrub and error counting. A scrub operation is performed at memory locations in a DRAM. The performing includes, for each of the memory locations: receiving a refresh command at the DRAM; executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and incrementing an error count in response to detecting an error during the executing. The method also includes comparing the error count to an error threshold. An alert is initiated in response to the error count exceeding the error threshold.

Abstract: Aspects of the invention include fetching data requested by a requestor from a primary memory in a memory system that includes the primary memory and a secondary memory mirroring the primary memory. An error status of the data fetched from the primary memory is determined. The error status is one of correctable error (CE), uncorrectable error (UE), and no error. Based at least in part on determining that the data fetched from the primary memory has the error status of no error, the data fetched from the primary memory is output to the requestor. Based at least in part on determining that the data fetched from the primary memory has the error status of UE or CE, the data requested by the requestor is fetched from the secondary memory.

Abstract: A technique relates to operating a memory controller. A feedback mode is initiated such that an identified memory device of first memory devices includes an identified bit lane on a data bus to be utilized for testing. A process includes sending commands on the 1-N bit lanes of the command address bus to a buffer and duplicating commands designated for a selected one of the 1-N bit lanes. The process includes sending the duplicated commands on the identified bit lane in route to the buffer, and receiving a result of a parity check for the commands sent on the 1-N bit lanes, such that when the result is a pass the process ends. When the result is a fail, a duplicated parity check is performed using duplicated commands on the identified bit lane in place of the selected one. When the duplicated parity check passes, the selected one is bad.

Abstract: An embodiment includes a method for use in operating a memory chip, the method comprising: operating the memory chip with an increased burst length relative to a standard burst length of the memory chip; and using the increased burst length to access metadata during a given operation of the memory chip. Another embodiment includes a memory module, comprising a plurality of memory chips, each memory chip being operable with an increased burst length relative to a standard burst length of the memory chip, the increased burst length being used to access metadata during a given operation of the memory module.

Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. The memory devices are characterized as one of a high or low random bit error rate (RBER) memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices, and common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The memory buffer device also includes refresh rate logic configured to adjust a refresh rate based on the detected error conditions.

Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM and executing error checking logic based on the data. The error checking logic detects an error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.

Abstract: A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.

Abstract: A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.

Abstract: An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller.

Abstract: A memory subsystem is disclosed comprising at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator receiving a power supply signal from a system power supply and outputting two or more power signals, each power signal providing a different, regulated voltage, which regulated voltages are each routed to each of the memory chips; and a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltages which are the same voltages as the voltages output by the voltage regulator on the memory module, and supplying the two or more signals to the memory module.

Abstract: An aspect includes receiving a request to access one or more memory devices in a stack of memory devices in a memory. Each of the memory devices are communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). A current operating mode of the memory is determined in response to receiving the request. Based at least in part on the current operating mode of the memory being a first mode, a chip select switch is activated to provide access to exactly one of the memory devices in the stack of memory devices. Based at least in part on the current operating mode of the memory being a second mode, the chip select switch is activated to access all of the memory devices in the stack in parallel. The request is serviced using the activated chip select switch.

Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.

Abstract: A memory subsystem is disclosed comprising at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator receiving a power supply signal from a system power supply and outputting two or more power signals, each power signal providing a different, regulated voltage, which regulated voltages are each routed to each of the memory chips; and a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltages which are the same voltages as the voltages output by the voltage regulator on the memory module, and supplying the two or more signals to the memory module.

Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.

Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

Abstract: Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.

Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.