Abstract: An aspect includes a method for dynamic random access memory (DRAM) scrub and error counting. A scrub operation is performed at memory locations in a DRAM. The performing includes, for each of the memory locations: receiving a refresh command at the DRAM; executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and incrementing an error count in response to detecting an error during the executing. The method also includes comparing the error count to an error threshold. An alert is initiated in response to the error count exceeding the error threshold.

Abstract: Keys are generated at a memory device with a period of time elapsing between generation of each key. A request is received from a memory controller for the most recently generated key. The memory device communicates the first key to the memory controller. Access to nonvolatile memory on the memory device is locked. An unlock command with a second key is received from the memory controller. The memory device determines that the second key matches the first key and unlocks access to the nonvolatile memory in response.

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Abstract: A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ECC) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ECC) bits and output the raw data and the ECC bits corresponding with memory addresses specified in the read command, and an ECC decoder to output an error vector associated with the memory addresses based on the raw data and the ECC bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses. The system also includes a multiplexer (MUX) to output the error vector based on a selection indicated in the read command.

Abstract: A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ECC) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ECC) bits and output the raw data and the ECC bits corresponding with memory addresses specified in the read command, and an ECC decoder to output an error vector associated with the memory addresses based on the raw data and the ECC bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses. The system also includes a multiplexer (MUX) to output the error vector based on a selection indicated in the read command.

Abstract: Keys are generated at a memory device with a period of time elapsing between generation of each key. A request is received from a memory controller for the most recently generated key. The memory device communicates the first key to the memory controller. Access to nonvolatile memory on the memory device is locked. An unlock command with a second key is received from the memory controller. The memory device determines that the second key matches the first key and unlocks access to the nonvolatile memory in response.

Abstract: Classifying memory errors may include accessing data from a location within a memory array of a memory device. The memory array may include at least one bit field to store memory error classification information. One or more memory errors in the data may be determined. One or more memory errors may further be classified. In response to the classifying, memory error classification information may be stored as one or more bit values within the bit field.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.

Abstract: A correctable memory error may be identified at a first address within a memory device. Based on at least the identifying, a first correctable memory error count may be updated from a first quantity to a second quantity. The second quantity may be determined to exceed or not exceed a threshold. In response to the determining, the first correctable memory error count of the second quantity may be: converted to a third quantity and reported to a host device accordingly, reported to a host device, or not reported to a host device.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Abstract: Embodiments disclosed herein generally relate to techniques for routing data through one or more cascaded memory modules. Each memory module can include a plurality of data buffers. Each data buffer includes a plurality of ports for routing data to and/or from other memory modules. In one embodiment, the data buffer is configured to route write data to DRAM devices on a first memory module or route write data to a data buffer of at least one downstream memory module. The data buffer is also configured to receive read data from a DRAM device of the first memory module or receive read data from a downstream memory module.

Abstract: Classifying memory errors may include accessing data from a location within a memory array of a memory device. The memory array may include at least one bit field to store memory error classification information. One or more memory errors in the data may be determined. One or more memory errors may further be classified. In response to the classifying, memory error classification information may be stored as one or more bit values within the bit field.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Abstract: A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.

Abstract: Keys are generated at a memory device with a period of time elapsing between generation of each key. A request is received from a memory controller for the most recently generated key. The memory device communicates the first key to the memory controller. Access to nonvolatile memory on the memory device is locked. An unlock command with a second key is received from the memory controller. The memory device determines that the second key matches the first key and unlocks access to the nonvolatile memory in response.