Abstract: Embodiments disclosed herein generally relate to techniques for routing data through one or more cascaded memory modules. Each memory module can include a plurality of data buffers. Each data buffer includes a plurality of ports for routing data to and/or from other memory modules. In one embodiment, the data buffer is configured to route write data to DRAM devices on a first memory module or route write data to a data buffer of at least one downstream memory module. The data buffer is also configured to receive read data from a DRAM device of the first memory module or receive read data from a downstream memory module.

Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM and executing error checking logic based on the data. The error checking logic detects and error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.

Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.

Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM from a memory controller and executing error checking logic based on the data. The error checking logic detects an error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached. The error condition is communicated to the memory controller in response to determining that detecting the error condition does not cause the error threshold to be reached.

Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.

Abstract: Embodiments of the present disclosure provide a method, computer program product, and system for monitoring a dynamic random-access memory (DRAM) device to detect and respond to a cryogenic attack. A processor receives a set of memory information about a DRAM device. The processor then determines a set of error indicators by processing the memory information using a set of decision parameters. The error indicators are then compared to an attack syndrome to determine if the DRAM is experiencing a cryogenic attack. If the DRAM is experiencing a cryogenic attack, access to the DRAM device is disabled.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition, where the write-back indicator is a discrete signal sent to a memory controller, and the at least one non-volatile memory device asserting the write-back indicator extends cycle timing monitored by the memory controller while the write-back indicator is asserted. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.

Abstract: Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.

Abstract: Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.

Abstract: Confirming memory marks indicating an error in computer memory including detecting, by memory logic responsive to a memory read operation, an error in at a memory location; marking, by the memory logic in an entry in a hardware mark table, the memory location as containing the error, the entry including one or more parameters for correcting the error; and retrying, by the memory logic, the memory read operation, including: responsive to again detecting the error in the memory location, determining whether the error is correctable at the memory location using the parameters included in the entry; and if the error is correctable at the memory location using the one or more parameters included in the entry, confirming the error in the entry of the hardware mark table.

Abstract: Managing entries in a mark table of computer memory errors including identifying at least two mark table entries as candidates for merger, wherein each mark table entry indicates an error at a location in a computer memory; and merging the identified mark table entries into a single mark table entry, including removing one of the identified mark table entries from the mark table.

Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

Abstract: Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.

Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM from a memory controller and executing error checking logic based on the data. The error checking logic detects and error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached. The error condition is communicated to the memory controller in response to determining that detecting the error condition does not cause the error threshold to be reached.

Abstract: An aspect includes coherency management between volatile memory and non-volatile memory in a through-silicon via (TSV) module of a computer system. A plurality of TSV write signals is simultaneously provided to the volatile memory and the non-volatile memory. A plurality of values of the TSV write signals is captured within a buffer of the non-volatile memory corresponding to a data set written to the volatile memory. Storage space is freed within the buffer as the data set corresponding to the values of the TSV write signals stored within the buffer is written to a non-volatile memory array within the non-volatile memory.