Patents by Inventor Warren E. Maule

Warren E. Maule has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ADAPTIVE ERROR CORRECTION IN A MEMORY SYSTEM
    Publication number: 20160036466
    Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 4, 2016
    Inventors: John K. DeBrosse, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Rona Yaari
  • ADAPTIVE ERROR CORRECTION IN A MEMORY SYSTEM
    Publication number: 20160034350
    Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.
    Type: Application
    Filed: August 25, 2015
    Publication date: February 4, 2016
    Inventors: John K. DeBrosse, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Rona Yaari
  • Accessing a resistive memory storage device
    Patent number: 9251894
    Abstract: Embodiments of the present disclosure describe a device and methods of accessing the device. The device can include a plurality of memory cells, each cell including a plurality of resistive memory components each designed to store data as resistance and an access transistor configured to control access to the plurality of resistive memory components. A wordline is configured to enable access to the set of resistor memory components by enabling the access transistor. A plurality of bitlines are each connected to a respective and different set of resistive memory components from each of the plurality of memory cells. A bitline controller is configured to access the plurality of resistive memory components by applying a first voltage to a first set of the plurality of bitlines and a second voltage to a second set of bitlines.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • ACCESSING A RESISTIVE MEMORY STORAGE DEVICE
    Publication number: 20150357033
    Abstract: Embodiments of the present disclosure describe a device and methods of accessing the device. The device can include a plurality of memory cells, each cell including a plurality of resistive memory components each designed to store data as resistance and an access transistor configured to control access to the plurality of resistive memory components. A wordline is configured to enable access to the set of resistor memory components by enabling the access transistor. A plurality of bitlines are each connected to a respective and different set of resistive memory components from each of the plurality of memory cells. A bitline controller is configured to access the plurality of resistive memory components by applying a first voltage to a first set of the plurality of bitlines and a second voltage to a second set of bitlines.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 10, 2015
    Inventors: Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • Error-correcting code distribution for memory systems
    Patent number: 9189327
    Abstract: According to one embodiment, a memory system includes a plurality of memory devices and a memory controller operatively coupled to the memory devices. The memory controller is configured to partition write data into a plurality of data blocks, where each data block is associated with one of the memory devices. The memory controller is further configured to generate an instance of a local error-correcting code (ECC) corresponding to each data block, and merge each data block with the corresponding instance of the local ECC to form an encoded data block for each memory device. Additionally, the memory controller is configured to write each encoded data block to the memory devices such that each memory device stores one of the data blocks with the corresponding instance of the local ECC. A global ECC and a local ECC of the global ECC can also be included in the memory system.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Kenneth L. Wright
  • Accessing a resistive memory storage device
    Patent number: 9159410
    Abstract: Embodiments of the present disclosure describe a device and methods of accessing the device. The device can include a plurality of memory cells, each cell including a plurality of resistive memory components each designed to store data as resistance and an access transistor configured to control access to the plurality of resistive memory components. A wordline is configured to enable access to the set of resistor memory components by enabling the access transistor. A plurality of bitlines are each connected to a respective and different set of resistive memory components from each of the plurality of memory cells. A bitline controller is configured to access the plurality of resistive memory components by applying a first voltage to a first set of the plurality of bitlines and a second voltage to a second set of bitlines.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • Securing the contents of a memory device
    Patent number: 9146883
    Abstract: A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule
  • Securing the contents of a memory device
    Patent number: 9146882
    Abstract: A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule
  • Implementing memory module communications with a host processor in multiported memory configurations
    Patent number: 9128834
    Abstract: A method, system and computer program product are provided for implementing ECC (Error Correction Codes) memory module communications with a host processor in multi-ported memory configurations in a computer system. Each of multiple memory modules operating in unison is enabled to identify which memory module is the one required to communicate module specific information back to the host processor. All of the multiple memory modules operating in unison are enabled to generate back to the host processor a valid ECC word, while other multiple memory modules individually being unaware of data contents of the one memory module required to communicate back to the processor.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: September 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: John S. Dodson, Luis A. Lastras-Montano, Warren E. Maule, Adam J. McPadden, Kenneth L. Wright
  • ERROR FEEDBACK AND LOGGING WITH MEMORY ON-CHIP ERROR CHECKING AND CORRECTING (ECC)
    Publication number: 20150212885
    Abstract: Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.
    Type: Application
    Filed: January 30, 2014
    Publication date: July 30, 2015
    Applicant: International Business Machines Corporation
    Inventors: Paul W. Coteus, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule, Vipinchandra Patel
  • ERROR FEEDBACK AND LOGGING WITH MEMORY ON-CHIP ERROR CHECKING AND CORRECTING (ECC)
    Publication number: 20150212886
    Abstract: Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.
    Type: Application
    Filed: June 30, 2014
    Publication date: July 30, 2015
    Inventors: Paul W. Coteus, Hillery C. Hunter, Charles Arthur Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule, Vipinchandra Patel
  • DETECTING DEFECTIVE CONNECTIONS IN STACKED MEMORY DEVICES
    Publication number: 20150179280
    Abstract: A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Applicant: International Business Machines Corporation
    Inventors: Charles A. Kilmer, Warren E. Maule, Saravanan Sethuraman
  • DETECTING DEFECTIVE CONNECTIONS IN STACKED MEMORY DEVICES
    Publication number: 20150179285
    Abstract: A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
    Type: Application
    Filed: April 9, 2014
    Publication date: June 25, 2015
    Applicant: International Business Machines Corporation
    Inventors: Charles A. Kilmer, Warren E. Maule, Saravanan Sethuraman
  • Implementing memory device with sub-bank architecture
    Patent number: 9064602
    Abstract: A method, system and memory controller are provided for implementing memory devices with sub-bank architecture in a computer system. An array is divided into sub-blocks having odd bit lines and even bit lines. The sub-blocks are alternated with rows of sense amplifiers; wherein a particular row of sense amplifiers connects only to odd bit lines and a next row of sense amplifiers connects only to even bit lines. More than one word line for a sub-block is allowed to be active at the same time, where a first active word line will select memory cells connected to even bit lines and a second active word line will select memory cells connected to odd bit lines.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: June 23, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • ERROR-CORRECTING CODE DISTRIBUTION FOR MEMORY SYSTEMS
    Publication number: 20150143201
    Abstract: According to one embodiment, a memory system includes a plurality of memory devices and a memory controller operatively coupled to the memory devices. The memory controller is configured to partition write data into a plurality of data blocks, where each data block is associated with one of the memory devices. The memory controller is further configured to generate an instance of a local error-correcting code (ECC) corresponding to each data block, and merge each data block with the corresponding instance of the local ECC to form an encoded data block for each memory device. Additionally, the memory controller is configured to write each encoded data block to the memory devices such that each memory device stores one of the data blocks with the corresponding instance of the local ECC. A global ECC and a local ECC of the global ECC can also be included in the memory system.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: International Business Machines Corporation
    Inventors: Paul W. Coteus, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Kenneth L. Wright
  • IMPLEMENTING MEMORY DEVICE WITH SUB-BANK ARCHITECTURE
    Publication number: 20150109874
    Abstract: A method, system and memory controller are provided for implementing memory devices with sub-bank architecture in a computer system. An array is divided into sub-blocks having odd bit lines and even bit lines. The sub-blocks are alternated with rows of sense amplifiers; wherein a particular row of sense amplifiers connects only to odd bit lines and a next row of sense amplifiers connects only to even bit lines. More than one word line for a sub-block is allowed to be active at the same time, where a first active word line will select memory cells connected to even bit lines and a second active word line will select memory cells connected to odd bit lines.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • IMPLEMENTING MEMORY MODULE COMMUNICATIONS WITH A HOST PROCESSOR IN MULTIPORTED MEMORY CONFIGURATIONS
    Publication number: 20150089279
    Abstract: A method, system and computer program product are provided for implementing ECC (Error Correction Codes) memory module communications with a host processor in multi-ported memory configurations in a computer system. Each of multiple memory modules operating in unison is enabled to identify which memory module is the one required to communicate module specific information back to the host processor. All of the multiple memory modules operating in unison are enabled to generate back to the host processor a valid ECC word, while other multiple memory modules individually being unaware of data contents of the one memory module required to communicate back to the processor.
    Type: Application
    Filed: September 24, 2013
    Publication date: March 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: John S. Dodson, Luis A. Lastras-Montano, Warren E. Maule, Adam J. McPadden, Kenneth L. Wright
  • MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE
    Publication number: 20140344514
    Abstract: A memory system with a programmable refresh cycle including a memory device. The memory device includes refresh circuitry in communication with a memory array and with a memory controller. The refresh circuitry is configured for receiving a refresh command from the memory controller and for refreshing a number of memory cells in the memory device in response to receiving the refresh command. A refresh cycle time of the refresh command is programmable. The memory device also includes a programmable refresh cycle mode register in communication with the refresh circuitry. Contents of the programmable refresh cycle mode register indicate the refresh cycle time of the refresh command.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 20, 2014
    Inventors: Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Vipin Patel
  • Implementing decoupling devices inside a TSV DRAM stack
    Patent number: 8890316
    Abstract: A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joab D. Henderson, Kyu-hyoun Kim, Warren E. Maule, Kenneth L. Wright
  • SECURING THE CONTENTS OF A MEMORY DEVICE
    Publication number: 20140223120
    Abstract: A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule