Abstract: A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.

Abstract: A method for fabricating a semiconductor device, such as a MOS (metal-oxide semiconductor) transistor, with self-aligned silicide is provided. This method can prevent junction leakage between the silicide and the substrate so as to allow the resultant semiconductor device to have reliable performance. The method includes the steps of preparing a semiconductor substrate; forming at least one transistor element over the substrate, the transistor element including a pair of source/drain regions, a gate, a dielectric layer over the gate, and a spacer on the sidewall of the gate; and performing an ion-bombardment process so as to transport one part of the dielectric layer that is adjacent to the top of the spacer to beside the bottom of the spacer.

Abstract: A post-CMP wafer clean process. A post-CMP wafer is provided. A portion of particles and slurry are removed from the wafer by double side scrubber. The residual particles and slurry are then removed from the wafer in a solvent tank by magasonic and a solvent in the solvent tank includes an amine-based compound.

Abstract: A multilevel interconnect structure is formed in a manner that reduces the problems associated with the formation and subsequent filling of unlanded vias. A first level wiring line is provided on the surface of an interlayer dielectric. The upper surface and sidewalls of the first level wiring line are covered with an etch stop material that is different from the intermetal dielectric used to separate the first level of wiring line from upper levels of wiring lines. The intermetal dielectric layer is deposited over the first level wiring line and a via is etched through the intermetal dielectric to expose the etch stop material above the wiring line, with the via etch stopping on the etch stop material. Etch stop material is removed to expose a portion of the upper surface of the wiring line and a metal plug is formed within the via and then an upper level wiring line is formed in contact with the metal plug.

Abstract: A method of fabricating a dual damascene structure. A low k dielectric layer and a cap layer are successively formed on a substrate having an active region. A first photoresist layer is formed on the cap layer and the cap layer is then patterned to expose a portion of the low k dielectric layer. The first photoresist layer and a portion of the low k dielectric layer are simultaneously removed to form a wiring line opening. A second photoresist layer is formed on the cap layer to cover a portion of the wiring line opening. When the step of removing the second photoresist layer is performed, a via hole is formed to expose the active region by simultaneously removing the exposed low k dielectric layer. The via hole and the wiring line opening are filled with a metal layer to form a wiring line and a via.

Abstract: A method of manufacturing embedded DRAM capable of integrating memory circuit regions and logic circuit regions together such that their top surfaces are at the same height, and hence able to maintain a high degree of planarity in integrated circuits. The method includes depositing a layer of refractory metal oxide over a high aspect ratio contact hole. Then, through the selective application of a hydrogen plasma treatment or hot hydrogen treatment, a portion of the deposited refractory metal oxide on the contact hole is transformed from non-conductive to conductive material, whereas the refractory metal oxide without a hydrogen plasma treatment or hot hydrogen treatment remains non-conductive. Therefore, a non-conductive refractory metal oxide layer can be used as a dielectric layer for a DRAM capacitor.

Abstract: A method for forming a self-aligned contact window such that the method is compatible with the process of forming a self-aligned titanium silicide layer on the same device, and hence capable of miniaturizing device dimensions. Furthermore, this invention utilizes the thicker etching stop layer thickness above the gate region than above the source/drain region to protect the titanium silicide layer in the gate region against electrical contact with the self-aligned contact.

Abstract: A method for fabricating trench isolation structures using the reverse mask is described. The method of using a reverse mask to fabricate trench isolation structures includes providing a semiconductor substrate having a first trench and a second trench in the substrate. The first trench has a width smaller than a fixed value, while the second trench has a width larger than the fixed value, the fixed value being, for example, about 0.7 .mu.m. Thereafter, a conformal insulating layer is formed over the first trench and the second trench. Next, a reverse mask layer is formed over the conformal insulating layer, and then the reverse mask layer is patterned. The reverse mask layer is patterned selectively. For example, only the region directly above the second trench is covered by the reverse mask. The region directly above the first trench is exposed.

Abstract: A method of forming a self-aligned salicide is provided. The invention twice performs selective epitaxial growth to form an amorphous silicon layer on gate electrodes and source/drain regions of a substrate after forming the gate electrodes and the source/drain regions. Then, a molybdenum impurity is doped to perform a silicidation process and to convert a metal deposited on the substrate into a salicide layer.

Abstract: The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and depositing a layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. A thin layer of amorphous silicon is then formed over the HSG-Si layer. This textured polysilicon structure forms the lower electrode of the DRAM capacitor. A dielectric layer is formed on the lower electrode, and an upper electrode is formed from a second layer of doped polysilicon. As-formed HSG-Si grains tend to form sharp intersections with the polysilicon layers on which they grow. When these HSG-Si grains are exposed to a thermal oxidation environment, poor quality oxides are formed at the sharp corners between the HSG-Si grains and the doped polysilicon layer.

Abstract: Silicidation of a polysilicon line having frcc upper sidewalls is performed so that no stress is applied to the sidewalls of the polysilicon line, resulting in the formation of a reduced stress silicide structure. This is accomplished by forming a polysilicon line having spacers on either side which extend above the upper surface of the polysilicon line but which are spaced from the edge of the polysilicon line. A layer of a metal such as titanium or tungsten is provided in contact with the top surface polysilicon line. The structure is annealed to cause the metal to react with the polysilicon to form a layer of silicide. Since the upper side portions of the polysilicon line are spaced away from the spacers during the silicidation anneal, the growing silicide region has room to expand without being subjected to lateral stresses in the silicidation process.

Abstract: A method of forming salicide, of which the characteristics is the formation of a silicon nitride layer before the source/drain being implanted with dopant. The silicon nitride layer avoid the oxygen within the oxide layer to implant into the source/drain. Thus, a better salicide is obtained. In addition, the formation of the parasitic spacers made of silicon nitride at the side wall bottom of the gate spacer increases the distance between the salicide and the junction. Consequently, the leakage current is prevented. While the silicon nitride layer is removed, the polysilicon of gate and the silicon of the source/drain are amorphized. This is advantageous to the formation of salicide without the step of ion implantation.

Abstract: The present invention provides a method of forming an undoped silicate glass layer on a semiconductor wafer by performing a high density plasma chemical vapor deposition process. The semiconductor wafer being positioned in a deposition chamber. The method comprises forming the undoped silicate glass layer by performing the high density plasma chemical vapor deposition process in the deposition chamber under the following conditions: an argon (Ar) flow rate of 40 to 70 sccm (standard cubic centimeter per minute); an oxygen (O.sub.2) flow rate of 90 to 120 sccm; a silane flow rate of 70 to 100 sccm; a gas pressure of 3 to 10 mtorr; a temperature of 300 to 400.degree. C.; and a low frequency power of 2500 to 3500 watts. Wherein the ratio of Ar to O.sub.2 is 0.53, and O.sub.2 to silane is 1.23.

Abstract: A method for adjusting the amount of doped nitride ions in a dielectric layer so that the nitride ions form bonds with silicon to increase the quality of an oxide layer. The method comprises the step of providing a silicon substrate. Next, a rapid thermal oxidation or furnace oxidation method is used to form an oxide layer over the silicon substrate. Gaseous mixtures having different ratios of nitrogen monoxide, nitrous oxide or ammonia to oxygen are concocted and then allowed to react at different reacting temperatures for controlling the nitride concentration level in the oxide layer. The nitride-doped oxide layer not only can stop the penetration of boron ions, but can also provide a stabilizing effect on the oxide layer/silicon substrate interface without degradation of electrical property, thereby improving the quality of a transistor.

Abstract: Salicide (self-aligned silicide) structures are formed using a process that does not form oxide spacer structures alongside polysilicon gate electrodes and wiring lines. A shaped polysilicon electrode is formed having protrusions extending beyond the sidewalls of the electrode. LDD source/drain regions are formed by ion implantation using only the polysilicon gate electrode as a mask, thereby forming LDD source drain/regions without using spacer oxide regions. Physical vapor deposition is used to deposit a metal layer having discontinuities at or adjacent the protrusions. A first rapid thermal anneal is performed to cause the metal to form a metal silicide over the polysilicon electrode. Unreacted metal is etched and then a second rapid thermal anneal is performed to convert the metal silicide to its lowest resistivity phase.

Abstract: The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-Si on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of three oxide layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out while keeping the substrate unbiased to form an oxide layer over the lines and in the gap. A second HDPCVD step in which the substrate is biased deposits a second oxide layer over the first oxide layer. During the second HDPCVD step some etching occurs and a portion of the first oxide layer is removed. A third HDPCVD step is carried out at a greater etch and sputtering rate than the second step to complete filling of the gap with dielectric material. The first oxide layer acts to protect the underlying structures from etching damage during the third step. Gaps between wiring lines can be filled with dielectric material without forming voids, even for high aspect ratio gaps.

Abstract: An antenna effect monitor includes a transistor formed on a semiconductor substrate. The transistor gate is coupled to a doped polysilicon interconnect layer which is also coupled to an antenna effect monitoring unit. Several metal bonding pads float in an orderly fashion above the doped polysilicon interconnect layer without coupling with each other. Several small metal layers are formed in an orderly fashion above the doped polysilicon interconnect layer but are electrically coupled together by several via plugs in between. The top small metal layer is coupled to the top bonding pad. The bottom small metal layer is electrically coupled to the doped polysilicon interconnect layer. Then a passivation layer covers the substrate but leaves a pad opening to expose the top bonding pad.

Abstract: A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure in an integrated circuit, which can prevent the occurrence of microscratches in the oxide plugs of the STI structure, thus further preventing the occurrence of a bridging effect and short-circuits between the circuit components that are intended to be electrically isolated by the STI structure. This method is characterized by the use of a laser annealing process to remove the microscratches that formed on the top surface of the oxide plugs during the chemical-mechanical polishing (CMP) process used to remove the upper part of the oxide layer to form the oxide plugs This method can therefore prevent the occurrence of a bridging effect and short-circuits due to the forming of the microscratches that would otherwise occur in the prior art.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation. A substrate having a plurality of active regions, including a large active region and a small active region, is provided. A silicon nitride layer is formed on the substrate. A shallow trench is formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trench is filled therewith. A partial reverse active mask is formed on the oxide layer, so that the oxide layer on a central part of the large active region is exposed. Whereas, the oxide layer on an edge part of the large active region and on the small active region are covered by the partial reverse active mask. The oxide layer is etched with the silicon nitride layer as a stop layer, using the partial reverse active mask as a mask. The oxide layer is planarized until the oxide layer within the shallow trench has a same level as the silicon nitride layer.