Patents by Inventor Water Lur

Water Lur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6251769
    Abstract: A method of manufacturing a contact pad. A substrate having a source/drain region formed therein is provided. A dielectric layer is formed over the substrate. An opening is formed in the dielectric layer and exposes the source/drain region. A selective epitaxial process is performed to form a contact pad in the opening, wherein a top of the contact pad extends onto a surface of the dielectric layer.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: June 26, 2001
    Assignee: United Microelectronics Corp
    Inventors: Tri-Rung Yew, Kuo-Tai Huang, Water Lur
  • Patent number: 6245380
    Abstract: A method of forming bonding pad commences by forming a conformal barrier layer on a provided inter-metal dielectric layer. A first metal layer is formed on the barrier layer to partially fill the trench. A thin glue layer is formed on the first metal layer. A second metal layer is formed on the glue layer to fill the trench. The second metal layer, the glue layer, the first metal layer and the barrier layer are partially removed to expose the dielectric layer. A bonding pad structure is thus formed in the trench. The bonding pad structure comprises a first metal pad and a second metal pad.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: June 12, 2001
    Assignee: United Microelectronics Corp
    Inventors: Shih-Wei Sun, Wen-Yi Hsieh, Water Lur, Kun-Chih Wang
  • Patent number: 6246119
    Abstract: A dual damascene structure includes a semiconductor substrate, a metal-oxide-semiconductor (MOS) transistor formed on the substrate and a metal layer. The metal layer is electrically connected to the conducting regions of the MOS transistor through interconnect. The metal layer further includes first metal spacing regions and second metal spacing regions, wherein the width of a first metal spacing region is about 1 to 10 times of the linewidth of the device, and the width of a second spacing region is about 0.8 to 1.2 times of the linewidth of the device. The first metal spacing regions includes a high-permittivity dielectric for a better thermal transferring rate, and the second spacing regions includes a low-permittivity dielectric for a shorter resistance-capacitance delay.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: June 12, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Juan-Yuan Wu, Water Lur
  • Publication number: 20010002335
    Abstract: A method for chemical mechanical polishing a component includes providing an oxide layer and forming at least one via through the oxide layer. A tungsten layer is formed within the via and over the oxide layer. A first chemical mechanical polishing step is carried out on a polishing pad using a first slurry having an oxidizing component and having a pH of approximately 2 to approximately 4 to remove the tungsten layer from over the oxide layer. A second chemical mechanical polishing step is carried out on the polishing pad using a second slurry having a pH of approximately 2 to approximately 4 to polish scratches out of the oxide layer.
    Type: Application
    Filed: November 24, 1997
    Publication date: May 31, 2001
    Inventors: MING-SHENG YANG, JUAN-YUAN WU, WATER LUR, SHIH-WEI SUN
  • Publication number: 20010002333
    Abstract: A method of fabricating a dual damascene is provided. A dielectric layer is formed on a substrate. A diffusion barrier layer is formed on the dielectric layer. A portion of the diffusion barrier layer and the dielectric layer is removed to form a trench and a via hole. A barrier layer is formed on the diffusion barrier layer and in the trench and the via hole. The barrier layer on the diffusion barrier layer is removed by chemical-mechanical polishing. A conductive layer is formed in the trench and the via hole by selective deposition. A planarization step is performed with the diffusion barrier layer serving as a stop layer.
    Type: Application
    Filed: March 29, 1999
    Publication date: May 31, 2001
    Inventors: CHAO-YUAN HUANG, JUAN-YUAN WU, WATER LUR
  • Patent number: 6238972
    Abstract: The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-Si on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: May 29, 2001
    Assignee: United Microelectronics Corporation
    Inventors: Tri-Rung Yew, Water Lur, Shih-Wei Sun
  • Patent number: 6239018
    Abstract: A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: May 29, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Juan-Yuan Wu, Water Lur
  • Publication number: 20010001191
    Abstract: A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.
    Type: Application
    Filed: January 2, 2001
    Publication date: May 17, 2001
    Inventors: Chih-Chien Liu, Juan-Yuan Wu, Water Lur
  • Patent number: 6232161
    Abstract: A method for fabricating a mask comprises a first pattern in respective of active areas, and a second pattern in respective of dummy active areas. After removing the first pattern, the profiles of the dummy active areas are enlarged. The N-well boundary and the P-well boundary of the second pattern is respectively shielded to form a first composed pattern and a second composed pattern comprising the larger dummy active areas and a shielding pattern. The dummy active areas on the substrate are shielded by the patterns of the embodiment during the process of ion implantation. Thus the resistivity of the dummy active areas is increased, whereby the parasitic capacitance can be prevented from being too large and affecting the performance of the devices.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: May 15, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Coming Chen, Water Lur
  • Patent number: 6228742
    Abstract: A method of fabricating a shallow trench isolation structure is described. A mask layer is formed on the substrate. The mask layer and the substrate are patterned to form trenches in the substrate. The trenches comprise a smallest trench. A first isolation layer is formed on the mask layer to fill partially the trenches. A densification step is performed. A second isolation layer is formed on the first isolation layer to fill completely the trench. The first isolation layer and the second isolation layer are removed until the mask layer is exposed. The mask layer is removed.
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: May 8, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Tri-Rung Yew, Water Lur, Gwo-Shii Yang
  • Patent number: 6228209
    Abstract: A fabrication equipment to form an opening plug is provided. The equipment at least includes a load/unload chamber, a degas chamber, an usual sputtering chamber, a radio frequency (RF) sputtering chamber, a physical vapor deposition (PVD) chamber, and a chemical vapor deposition (CVD). The load/unload chamber is used to load a substrate. The degas chamber is used to remove moisture on the substrate. The usual sputtering chamber is used to form an opening on the substrate. The PVD chamber is used to form a first glue layer. The RF sputtering chamber is used to remove an overhang structure on the first glue layer. The CVD chamber is used to form a second glue layer over the first glue layer.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: May 8, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Coming Chen, Juan-Yuan Wu, Water Lur
  • Patent number: 6218284
    Abstract: A method for forming an inter-metal dielectric layer without voids therein is described. Wiring lines are formed on a provided substrate. Each of the wiring lines comprises a protective layer thereon. A liner layer is formed over the substrate and over the wiring lines. A fluorinated silicate glass (FSG) layer is formed on the liner layer by using high density plasma chemical vapor deposition (HDPCVD). A thickness of the FSG layer is about 0.9-1 times a thickness of the wiring lines. A cap layer is formed on the FSG layer using HDPCVD. A thickness of the cap layer is about 0.2-0.3 times a thickness of the wiring lines. An oxide layer is formed on the cap layer to achieve a predetermined thickness. A part of the dielectric layer is removed to obtain a planarized surface.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: April 17, 2001
    Assignee: United Microelectronics, Corp.
    Inventors: Chih-Chien Liu, Cheng-Yuan Tsai, Wen-Yi Hsieh, Water Lur
  • Patent number: 6214745
    Abstract: A chemical-mechanical polishing method utilizes a shallow dummy pattern for planarizing a dielectric layer. The method includes the steps of first forming a shallow dummy pattern on the dielectric layer, and then coating a patterned photoresist layer over the dielectric layer. Thereafter, the photoresist layer is used as a mask to form openings in other areas of the dielectric layer. Subsequently, the photoresist layer is removed to expose the shallow dummy pattern, and then a glue/barrier layer and a conductive layer are sequentially deposited. Next, a chemical-mechanical polishing operation is carried out to remove excess conductive layer and glue/barrier layer above the dielectric layer as well as the shallow dummy pattern at the same time. Since the removal rate of glue/barrier layer in each area above the dielectric layer is about the same, a planar substrate surface is obtained.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: April 10, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Sheng Yang, Yimin Huang, Juan-Yuan Wu, Water Lur
  • Patent number: 6214691
    Abstract: A method for forming shallow trench isolation is disclosed. The method includes forming a trench in a semiconductor substrate, and then blanket depositing a silicon oxide layer over the semiconductor substrate by a plasma process, thereby substantially refilling the trench. Thereafter, a photoresist layer is formed on the plasma deposited silicon oxide layer, followed by etching back a portion of the photoresist layer. The plasma deposited silicon oxide layer is then isotropically etched, and the photoresist layer is then finally removed.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: April 10, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Gwo-Shii Yong, Chih-Chien Liu, Tri-Rung Yew, Water Lur
  • Patent number: 6203863
    Abstract: A method of gap filling by using HDPCVD. On a substrate having a conductive structure, a first oxide layer is formed to protect the conductive structure. While forming the first oxide layer no bias is applied. An argon flow with a high speed of etching/deposition is provided to form a second oxide layer. While forming the second oxide layer a triangular or trapezium profile is formed due to an etching effect to the corner. An argon flow with a low speed of etching/deposition is provided to form a third oxide layer. The gap filling is completed.
    Type: Grant
    Filed: November 27, 1998
    Date of Patent: March 20, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
  • Patent number: 6180492
    Abstract: An improved method for forming shallow trench isolation structure is described. The present method comprises the steps of providing a pad oxide layer and a mask layer on a semiconductor substrate and forming a trench structure therein. Next, a liner oxide layer is formed on the surface of the trench structure in the semiconductor substrate and is extensively formed on the side surface of the mask layer exposed therein and the top surface of the mask layer by wet oxidation. A dielectric material is deposited on the liner oxide layer and fills the trench structure. The dielectric material layer is planarized. The mask layer and the pad oxide layer are then removed to form the isolation structures. The method for forming the shallow trench structures on a semiconductor structure in accordance with the present invention can eliminate the kink effect that occurs in the conventional method.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: January 30, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Hsueh-Hao Shih, Tri-Rung Yew, Water Lur, Gwo-Shii Yang
  • Patent number: 6180451
    Abstract: A method of forming a DRAM capacitor. A hemispherical grain structure is formed on the surface of the bottom electrode of the capacitor. By employing an additional annealing under a dopant contained ambient, the dopant is diffused into the hemispherical grain structure and distributed at the surface area of the hemispherical grain region.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: January 30, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Yi Hsieh, Juan-Yuan Wu, Water Lur
  • Patent number: 6178543
    Abstract: A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: January 23, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Coming Chen, Juan-Yuan Wu, Water Lur
  • Patent number: 6174812
    Abstract: A copper-palladium alloy damascene technology applied to the ultra large scale integration (ULSI) circuits fabrication is disclosed. First, a TaN barrier is deposited over an oxide layer or in terms of the inter metal dielectric (IMD) layer. Then a copper-palladium seed is deposited over the TaN barrier. Furthermore, a copper-palladium gap-fill electroplating layer is electroplated over the dielectric oxide layer. Second, a copper-palladium annealing process is carried out. Then the copper-palladium electroplating surface is planarized by means of a chemical mechanical polishing (CMP) process. Third, the CoWP cap is self-aligned to the planarized copper-palladium alloy surface. Finally, a second IMD layer is deposited over the first IMD layer. Furthermore, a contact hole in the second dielectric layer over said CoWP cap layer is formed, and then the CoWP cap of the first IMD layer is connected with the copper-palladium alloy bottom surface of the second IMD layer directly.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: January 16, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Chiung-Sheng Hsiung, Wen-Yi Hsieh, Water Lur
  • Patent number: 6171899
    Abstract: A method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. The dielectric film can be a mono-layer structure or a multi-layer structure comprising various dielectric materials. A rapid thermal process (RTP), such as a rapid thermal annealing, or a plasma treatment is performed to enhance the quality of the dielectric film. A photolithography and etching process is performed to remove a part of the dielectric film and the first metal layer to expose a part of the inter-layer dielectric layer. The remaining first conductive layer is used as a lower electrode. A conventional interconnect process is performed on the exposed inter-layer dielectric layer and on the dielectric film. For example, a glue layer is formed on the exposed inter-layer dielectric layer and on the dielectric film. A second metal layer is formed on the glue layer.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: January 9, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Fu-Tai Liou, Water Lur, Kuan-Cheng Su, Juan-Yuan Wu