Abstract: The present disclosure describes systems, methods, and non-transitory computer readable media for detecting user interactions to edit a digital image from a client device and modify the digital image for the client device by using a web-based intermediary that modifies a latent vector of the digital image and an image modification neural network to generate a modified digital image from the modified latent vector. In response to user interaction to modify a digital image, for instance, the disclosed systems modify a latent vector extracted from the digital image to reflect the requested modification. The disclosed systems further use a latent vector stream renderer (as an intermediary device) to generate an image delta that indicates a difference between the digital image and the modified digital image. The disclosed systems then provide the image delta as part of a digital stream to a client device to quickly render the modified digital image.

Abstract: Disclosed herein are novel polyhydroxylated indolizidine and pyrrolizidine derivates and methods for using the same in the treatment of cancer. The present polyhydroxylated indolizidine and pyrrolizidine derivates has the structure of formula (I), wherein: X is O or b and c are independently an integral of 0 or and 1; R is selected from the group consisting of H, C1-6 alkyl, alkenyl, alkynyl, aryl, heteroaryl, cycloalkyl, cycloalkenyl, aralkyl, aralkenyl, aralkynyl, heteroaralkyl, heteroaralkenyl, beteroaralkynyl, heterocyclyl, alkoxy, aryloxy, and sulfonyl.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: An electrode-modified heavy metal ion microfluidic detection chip, comprising a microfluidic module (1) and a three-electrode sensor (2), wherein the microfluidic module (1) is integrally molded by 3D printing, and the interior thereof has a microchannel (10) and a sensor slot (11); and the three-electrode sensor (2) comprises three electrodes (21, 22, 23) printed on a card-shaped bottom plate (20), among which the working electrode (21) is a porous nano-NiMn2O4 modified bare carbon electrode, and the three-electrode sensor (2) is inserted into the sensor slot (11) that matches same to form the microfluidic detection chip.

Abstract: The present invention provides an electric tool comprising a body, an operating component, an output shaft, and a stop mechanism. An arresting disc is disposed on the output shaft, and a groove is formed on the arresting disc; the stop mechanism comprises a protrusion, for example, a pin, which is operable so that the protrusion extends to insert into the groove to lock the output shaft. A stop mechanism of the present invention is easy to operate, delivers good safety performance, and has a relatively simple structure, which allows convenient production and subsequent maintenance. Further, a stop mechanism of the present invention automatically springs back to a non-stop position at which it detaches from the output shaft or the transmission gear of the transmission mechanism when the external force is lost, which prevents possible damage to the output shaft or transmission mechanism when a user starts the electric tool before releasing the stop mechanism.

Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.

Abstract: An integrated circuit includes a horizontal routing track in a first metal layer, and a backside routing track in a backside metal layer. The backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. The horizontal routing track is conductively connected to a first terminal of a first transistor without passing through a routing track in another metal layer. The backside routing track is conductively connected to a second terminal of the first transistor without passing through a routing track in another metal layer. One of the first terminal and the second terminal is a gate terminal of the first transistor while another one the first terminal and the second terminal is either a source terminal or a drain terminal of the first transistor.

Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.

Abstract: Systems and methods dynamically adjust an available range for editing an attribute in an image. An image editing system computes a metric for an attribute in an input image as a function of a latent space representation of the input image and a filtering vector for editing the input image. The image editing system compares the metric to a threshold. If the metric exceeds the threshold, then the image editing system selects a first range for editing the attribute in the input image. If the metric does not exceed the threshold, a second range is selected. The image editing system causes display of a user interface for editing the input image comprising an interface element for editing the attribute within the selected range.

Abstract: A negative electrode structure applied to an aluminum battery includes a hole material layer and a metal plating layer. The metal plating layer is located on the hole material layer such that the capacity decay rate of the aluminum battery is less than 5% per cycle.

Abstract: A semiconductor device includes a first semiconductor die and a second semiconductor die connected to the first semiconductor die. Each of the first semiconductor die and the second semiconductor die includes a substrate, a conductive bump formed on the substrate and a conductive contact formed on the conductive bump. The conductive contact has an outer lateral sidewall, there is an inner acute angle included between the outer lateral sidewall and the substrate is smaller than 85°, and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die.

Abstract: An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.

Abstract: An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell.

Abstract: Systems and methods for facial image generation are described. One aspect of the systems and methods includes receiving an image depicting a face, wherein the face has an identity non-related attribute and a first identity-related attribute; encoding the image to obtain an identity non-related attribute vector in an identity non-related attribute vector space, wherein the identity non-related attribute vector represents the identity non-related attribute; selecting an identity-related vector from an identity-related vector space, wherein the identity-related vector represents a second identity-related attribute different from the first identity-related attribute; generating a modified latent vector in a latent vector space based on the identity non-related attribute vector and the identity-related vector; and generating a modified image based on the modified latent vector, wherein the modified image depicts a face that has the identity non-related attribute and the second identity-related attribute.

Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.

Abstract: An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.

Abstract: A pixel unit includes a red LED chip, a green LED chip, and a blue LED chip. Each of these chips has an optical density concentration zone and a reference line passing through the geometric center of the top-view shape of the chip. The optical density concentration zone of each of these chips is deviated to one side of the respective reference line of the chip. The reference lines of the chips are parallel to each other. The optical density concentration zones of the chips are all deviated to the same side of the respective reference line.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: An integrated circuit includes a first transistor, a horizontal routing track extending in a first direction in a first metal layer, and a via connector conductively connecting the horizontal routing track to a first terminal of the first transistor. The integrated circuit also includes a backside routing track extending in the first direction in a backside metal layer, and a backside via connector conductively connecting the backside routing track to a second terminal of the first transistor. The backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. In the integrated circuit, either the first terminal or the second terminal is a gate terminal of the first transistor.

Abstract: A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.