Patents by Inventor Wei An

Wei An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230332277
    Abstract: The present disclosure discloses an aluminum alloy, based on a total mass of the aluminum alloy, including: 9-12% Si; 3.0-5.0% Zn; 1.5-2.6% Cu; 0.4-0.9% Mn; 0.2-0.6% Mg; 0.1-0.25% Fe; 0.03-0.35% Zr; 0.05-0.2% Ti; 0.005-0.04% Sr; 0.01-0.02% Ga; 0.005-0.01% Mo; 0.001-0.02% Cr; 0.005-0.3% Ni; 78.01-85.624% Al; and an impurity element.
    Type: Application
    Filed: June 21, 2023
    Publication date: October 19, 2023
    Inventors: Qiang GUO, Mengde WANG, Wei AN
  • Publication number: 20230317564
    Abstract: A semiconductor package includes a first integrated circuit, a plurality of first through vias and a plurality of fin-shaped through vias. The first through vias surround the first integrated circuit. The fin-shaped through vias are physically connected to the first through vias respectively, wherein the first through vias are disposed between the first integrated circuit and the fin-shaped through vias.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Wei-An Tsao, Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20230316475
    Abstract: An item recommendation system receives a set of recommendable items and a request to select, from the set of recommendable items, a contrast group. The item recommendation system selects a contrast group from the set of recommendable items by applying a image modification model to the set of recommendable items. The image modification model includes an item selection model configured to determine an unbiased conversion rate for each item of the set of recommendable items and select a recommended item from the set of recommendable items having a greatest unbiased conversion rate. The image modification model includes a contrast group selection model configured to select, for the recommended item, a contrast group comprising the recommended item and one or more contrast items. The item recommendation system transmits the contrast group responsive to the request.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Cameron Smith, Wei-An Lin, Timothy M. Converse, Shabnam Ghadar, Ratheesh Kalarot, John Nack, Jingwan Lu, Hui Qu, Elya Shechtman, Baldo Faieta
  • Publication number: 20230316606
    Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for latent-based editing of digital images using a generative neural network. In particular, in one or more embodiments, the disclosed systems perform latent-based editing of a digital image by mapping a feature tensor and a set of style vectors for the digital image into a joint feature style space. In one or more implementations, the disclosed systems apply a joint feature style perturbation and/or modification vectors within the joint feature style space to determine modified style vectors and a modified feature tensor. Moreover, in one or more embodiments the disclosed systems generate a modified digital image utilizing a generative neural network from the modified style vectors and the modified feature tensor.
    Type: Application
    Filed: March 21, 2022
    Publication date: October 5, 2023
    Inventors: Hui Qu, Baldo Faieta, Cameron Smith, Elya Shechtman, Jingwan Lu, Ratheesh Kalarot, Richard Zhang, Saeid Motiian, Shabnam Ghadar, Wei-An Lin
  • Publication number: 20230316474
    Abstract: Methods, systems, and non-transitory computer readable media are disclosed for intelligently enhancing details in edited images. The disclosed system iteratively updates residual detail latent code for segments in edited images where detail has been lost through the editing process. More particularly, the disclosed system enhances an edited segment in an edited image based on details in a detailed segment of an image. Additionally, the disclosed system may utilize a detail neural network encoder to project the detailed segment and a corresponding segment of the edited image into a residual detail latent code. In some embodiments, the disclosed system generates a refined edited image based on the residual detail latent code and a latent vector of the edited image.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Inventors: Hui Qu, Jingwan Lu, Saeid Motiian, Shabnam Ghadar, Wei-An Lin, Elya Shechtman
  • Publication number: 20230307365
    Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 28, 2023
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Yi-Hsun Chiu, Yi-Bo Liao, Kuan-Lun Cheng, Wei-Cheng Lin, Wei-An Lai, Ming Chian Tsai, Jiann-Tyng Tzeng, Hou-Yu Chen, Chun-Yuan Chen, Huan-Chieh Su
  • Patent number: 11769723
    Abstract: A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin, Wei-An Lai
  • Patent number: 11756876
    Abstract: A semiconductor device includes a base, source, drain and gate electrodes, signal tracks and a power mesh. The source, drain and gate electrodes are arranged on a surface of the base, wherein the gate electrodes are extended along a first direction. The signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes, wherein the signal tracks are extended along the first directions. A power mesh is arranged below the first surface of the base, the power mesh comprising first power rails extended in the second direction and second power rails extended in a first direction, wherein the second direction is substantially perpendicular to the first direction.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-An Lai, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Patent number: 11737254
    Abstract: A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Hsin Chiu, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-An Lai
  • Publication number: 20230259685
    Abstract: A layout method includes: providing a library comprising a first cell and a second cell, wherein each of the first and second cells includes: a first active region and a second active region extending in a first direction; a first cell-edge gate structure and a second cell-edge gate structure extending in a second direction; and a third cell-edge gate structure and a fourth cell-edge gate structure extending in the second direction, wherein each of the first and second cell further includes one of a tie-off conductive line or a tie-off marker layer on each of the first and second cell-edge gate structures. The layout method further includes: generating a design layout by placing and abutting the first cell and the second cell; updating the design layout by performing a post-processing step on the tie-off conductive line and the tie-off marker layer of each of the first and second cells.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Inventors: JIANN-TYNG TZENG, SHIH-WEI PENG, MENG-HUNG SHEN, WEI-AN LAI
  • Patent number: 11727614
    Abstract: The present disclosure describes systems, methods, and non-transitory computer readable media for detecting user interactions to edit a digital image from a client device and modify the digital image for the client device by using a web-based intermediary that modifies a latent vector of the digital image and an image modification neural network to generate a modified digital image from the modified latent vector. In response to user interaction to modify a digital image, for instance, the disclosed systems modify a latent vector extracted from the digital image to reflect the requested modification. The disclosed systems further use a latent vector stream renderer (as an intermediary device) to generate an image delta that indicates a difference between the digital image and the modified digital image. The disclosed systems then provide the image delta as part of a digital stream to a client device to quickly render the modified digital image.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: August 15, 2023
    Assignee: Adobe Inc.
    Inventors: Akhilesh Kumar, Baldo Faieta, Piotr Walczyszyn, Ratheesh Kalarot, Archie Bagnall, Shabnam Ghadar, Wei-An Lin, Cameron Smith, Christian Cantrell, Patrick Hebron, Wilson Chan, Jingwan Lu, Holger Winnemoeller, Sven Olsen
  • Patent number: 11721576
    Abstract: A method includes: doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Te-Hsin Chiu, Shih-Wei Peng, Wei-An Lai, Jiann-Tyng Tzeng
  • Publication number: 20230231132
    Abstract: An aluminum battery negative electrode structure includes an aluminum foil and a coating layer. The coating layer is arranged on the aluminum foil. A material of the coating layer includes a high specific surface area carbon material. A specific surface area of the high specific surface area carbon material ranges from 500 m2/g to 3,000 m2/g.
    Type: Application
    Filed: November 2, 2022
    Publication date: July 20, 2023
    Applicant: APh ePower Co., Ltd.
    Inventors: Jui-Hsuan Wu, Shih Po Ta Tsai, Yi Hsiu Wang, Wei-An Chen
  • Publication number: 20230193429
    Abstract: An aluminum alloy and application thereof are disclosed. Based on a total mass of the aluminum alloy, the aluminum alloy includes: 7%-11% Si, 0.4%-1.0% Fe, 0.001%-0.2% Mg, 0.001%-0.2% Cu, 0.001%-0.2% Zn, 0.005%-0.1% Mn, 0.01%-0.06% Sr, 0.003%-0.05% B, 0.01%-0.02% Ga, 0.001%-0.01% Mo, 0.001%-0.2% Ce, 0.0003%-0.02% La, and balanced by aluminum and impurity elements, where a total amount of the impurity elements is less than 0.1%.
    Type: Application
    Filed: February 23, 2023
    Publication date: June 22, 2023
    Inventors: Qiang GUO, Mengde WANG, Wei AN, Jingsong FU
  • Patent number: 11658119
    Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Yi-Hsun Chiu, Yi-Bo Liao, Kuan-Lun Cheng, Wei-Cheng Lin, Wei-An Lai, Ming Chian Tsai, Jiann-Tyng Tzeng, Hou-Yu Chen, Chun-Yuan Chen, Huan-Chieh Su
  • Publication number: 20230154088
    Abstract: Systems and methods for image processing are described. Embodiments of the present disclosure encode features of a source image to obtain a source appearance encoding that represents inherent attributes of a face in the source image; encode features of a target image to obtain a target non-appearance encoding that represents contextual attributes of the target image; combine the source appearance encoding and the target non-appearance encoding to obtain combined image features; and generate a modified target image based on the combined image features, wherein the modified target image includes the inherent attributes of the face in the source image together with the contextual attributes of the target image.
    Type: Application
    Filed: November 17, 2021
    Publication date: May 18, 2023
    Inventors: Kevin Duarte, Wei-An Lin, Ratheesh Kalarot, Shabnam Ghadar, Jingwan Lu, Elya Shechtman, John Thomas Nack
  • Publication number: 20230154846
    Abstract: A method of making a semiconductor structure includes defining a first recess in an insulation layer. The method further includes forming a protection layer along a sidewall of the first recess. The method further includes forming a first conductive line in the first recess and in direct contact with the protection layer. The method further includes depositing a first insulation material over the first conductive line. The method further includes defining a second recess in the first insulation material. The method further includes forming a second conductive line in the second recess. The method further includes forming a via extending from the second conductive line, wherein the via directly contacts a sidewall of the protection layer.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 18, 2023
    Inventors: Te-Hsin CHIU, Wei-An LAI, Meng-Hung SHEN, Wei-Cheng LIN, Jiann-Tyng TZENG, Kam-Tou SIO
  • Patent number: 11649528
    Abstract: The present disclosure relates to a copper based microcrystalline alloy and a preparation method thereof, and an electronic product. In percentage by weight and based on the total amount of the copper based microcrystalline alloy, the copper based microcrystalline alloy includes: 30-60 wt % of Cu; 25-40 wt % of Mn; 4-6 wt % of Al; 10-17 wt % of Ni; 0.01-10 wt % of Si; and 0.001-0.03% of Be.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: May 16, 2023
    Assignee: BYD COMPANY LIMITED
    Inventors: Qing Gong, Qiang Guo, Mengde Wang, Wei An
  • Publication number: 20230105701
    Abstract: Provided is a dissolution-enhanced olaparib composition, a preparation method therefor, a use thereof, and a medicament including the dissolution-enhanced olaparib composition. The dissolution-enhanced olaparib composition includes: olaparib; copovidone and a dissolution enhancer, wherein based on 100 parts by weight of olaparib, 100 or more and less than 200 parts by weight of copovidone, and 20 to 150 parts by weight of a dissolution enhancer. The dissolution-enhanced olaparib composition and the medicament prepared therefrom have controllable stability, increased oral absorption of the active ingredient, reduced excipient dosage, improved medication convenience, and are easy for industrial production.
    Type: Application
    Filed: March 4, 2021
    Publication date: April 6, 2023
    Inventors: Yong GAN, Shiyan GUO, Wei AN
  • Patent number: 11569166
    Abstract: The present disclosure provides a semiconductor structure, including a substrate, a first metal line over the substrate and extending along a first direction, a protection layer lining a sidewall of the first metal line, a second metal line above the first metal line and extending along the first direction, and a third metal line above the second metal line, extending along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Wei-An Lai, Meng-Hung Shen, Wei-Cheng Lin, Jiann-Tyng Tzeng, Kam-Tou Sio