Abstract: A semiconductor device includes a substrate having a first planar region, a second planar region adjacent to the first planar region, a non-planar region between the first planar region and the second planar region, a first base on the first planar region, a second base on the second planar region, and a plurality of bumps on the non-planar region. Preferably, the bumps have different heights, top surfaces of the first base and the second base are coplanar, the top surface of the bumps is lower than the top surface of the first base, and the height of the bumps closer to the first planar region is greater than the height of the bumps closer to the non-planar region.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.

Abstract: A connector assembly includes a guiding shield cage and a plurality of supporting seats. The guiding shield cage includes an outer shell and a plurality of supporting seat fixing portions which are formed to a bottom end of the outer shell, each supporting seat fixing portion includes a first engaging portion and a first supporting portion. The plurality of supporting seats are respectively assembled to the plurality of supporting seat fixing portions, each supporting seat includes a second engaging portion and a second supporting portion; the second engaging portion and the first engaging portion are engaged with and fixed to each other, the second supporting portion supports the first supporting portion relative to a direction that the outer shell is toward the down.

Abstract: A reflective mask includes a substrate, a lower reflective multilayer disposed over the substrate, an intermediate layer disposed over the lower reflective multilayer, an upper reflective multilayer disposed over the intermediate layer, a capping layer disposed over the upper reflective multilayer, and an absorber layer disposed in a trench formed in the upper reflective layers and over the intermediate layer. The intermediate layer includes a metal other than Cr, Ru, Si, Si compound and carbon.

Abstract: A cavity mold-replacing structure of a parallel crimping plier is provided. The structure includes a first crimping component having a first clamping handle and a crimping portion with a crimping opening; a second clamping handle having a first pivot member and a second clamping handle; a mold-pressing component including an upper mold-pressing member and a lower mold-pressing member; wherein the upper mold-pressing member is fixed at top of the crimping opening, and the lower mold-pressing member is pivot with the other end of the first pivot member and disposed below the crimping opening; and a mold-replacing component, having a mold-replacing block movably disposed in the internal space of the crimping portion and the mold-replacing block can be moved.

Abstract: The invention provides a touch display panel and a manufacturing method therefor. The touch display panel comprises a substrate; a display region disposed on the substrate; a first touch electrode disposed in the display region; a second touch electrode disposed in the display region; and a third touch electrode disposed in the display region, the first touch electrode, the second touch electrode and the third touch electrode arranged adjacently, and the third touch electrode and the second touch electrode electrically disconnected; wherein the second touch electrode is electrically connected to the first touch electrode, and an area of the third touch electrode is greater than an area of the first touch electrode and/or an area of the second touch electrode.

Abstract: The disclosure provides a voltage control device for controlling supply voltages of a power amplifier (PA). The voltage control device includes a first processing circuit to provide a first supply voltage to at least one driving stage amplifier of the PA, and a second processing circuit to provide a second supply voltage to an output stage amplifier of the PA. The first supply voltage is generated according to an average-power-tracking (APT) mechanism related to an average power level of a radio frequency (RF) signal transmitted by the PA.

Abstract: Provided are a detection system, compensation method and computer-readable recording medium applicable to semiconductor surface morphology to provide feature information corresponding to spectral signals to a neural network model and provide feature information corresponding to spectral signals, a detected height, and an actual height actually measured to another neural network model. The combinational neural network models thus trained and built can generate a compensation value for a to-correct height corresponding to a to-correct spectral signal having variability. The compensation value provides required compensation for height information to not only enhance the precision of the detection of semiconductor surface morphology but also enhance the reliability of the detection system.

Abstract: A semiconductor structure includes a substrate, a trench, a first conductive layer, a second conductive layer, a third conductive layer, a source region and a drain region, a bit line contact, and a storage node contact. The trench is disposed in the substrate. The first conductive layer is disposed in the trench. The second conductive layer is disposed on a top surface of the first conductive layer. The third conductive layer is disposed on the top surface of the first conductive layer and is electrically connected to the second conductive layer. The source region and the drain region are disposed in the substrate and disposed on opposite sides of the first conductive layer. The bit line contact is disposed on one of the source region and the drain region, and the storage node contact is disposed on the other of the source region and the drain region.

Abstract: A semiconductor structure includes a substrate and a dielectric material disposed over the substrate. A void is disposed within the dielectric material. A dielectric liner is disposed along inner sidewalls of the dielectric material proximate to the void. An inner surface of the dielectric liner defines an outer extent of the void, and the dielectric liner includes an inner liner layer and an outer liner layer.

Abstract: The present invention provides a polyimide film, which comprises a polyimide having a structure represented by formula (I): in which A is a residue group of an aromatic diamine containing a sulfonyl group in its main chain moiety, R1 is a residue group of an aromatic dianhydride, R2 is a residue group of an aliphatic dianhydride, m and n are each independently a positive integer, a diamine monomer constituting the polyimide is only composed of the aromatic diamine containing the sulfonyl group in its main chain moiety, and the polyimide is surface-dried at 75° C. to 155° C. in the process of forming the polyimide film. The polyimide film of the present invention has transparency and UV absorption properties.

Abstract: An imaging lens includes a light blocking sheet that includes an inner ring surface, a plurality of tapered light blocking structures, and a nanostructure layer. The inner ring surface surrounds an optical axis and defines a light passage opening. The tapered light blocking structures are disposed on the inner ring surface, and each tapered light blocking structure protrudes from the inner ring surface and tapers off towards the optical axis. The tapered light blocking structures are periodically arranged to surround the optical axis. The contour of each tapered light blocking structure has a curved part in a view along the optical axis. The curved part forms a curved surface on the inner ring surface. The nanostructure layer is disposed on the curved surface and has a plurality of ridge-like protrusions that extend non-directionally, and the average structure height of the nanostructure layer ranges from 98 nanometers to 350 nanometers.

Abstract: The invention provides a touch display panel and a manufacturing method therefor. The touch display panel comprises a substrate; a display region disposed on the substrate; a first touch electrode disposed in the display region; a second touch electrode disposed in the display region; and a third touch electrode disposed in the display region, the first touch electrode, the second touch electrode and the third touch electrode arranged adjacently, and the third touch electrode and the second touch electrode electrically disconnected; wherein the second touch electrode is electrically connected to the first touch electrode, and an area of the third touch electrode is greater than an area of the first touch electrode and/or an area of the second touch electrode.

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

Abstract: A method for forming a semiconductor structure includes the following steps. A first trench is formed in a semiconductor substrate, and a first nitride layer is formed along a sidewall and a bottom surface of the first trench. A first oxide layer is formed over the first nitride layer to fill the first trench, and the first oxide layer is recessed from the first trench to form a first recess. A portion of the first nitride layer exposed from the first recess is etched, and a second nitride layer is formed along a sidewall and a bottom surface of the first recess. The second nitride layer includes a first portion along the bottom surface and a second portion along the sidewall. The second portion is removed, and a second oxide layer is formed over the first portion to fill the first recess.

Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.

Abstract: An imaging lens assembly includes a plurality of lens elements, a light path folding element and a sheet-like light blocking element. An optical axis is defined via the lens elements. The light path folding element includes an optical surface, and a total reflection of an imaging light of the imaging lens assembly occurs at least once on the optical surface. The sheet-like light blocking element is corresponding to the light path folding element, and the sheet-like light blocking element includes a first surface, a second surface and a microstructure layer. The first surface faces towards the optical surface. The second surface is disposed relatively to the first surface. The microstructure layer is at least disposed on the first surface, and protrusions are formed on the first surface via the microstructure layer. At least partial area between the microstructure layer and the optical surface has an air slit.

Abstract: A semiconductor structure includes a substrate and a dielectric material disposed over the substrate. A void is disposed within the dielectric material. A dielectric liner is disposed along inner sidewalls of the dielectric material proximate to the void. An inner surface of the dielectric liner defines an outer extent of the void, and the dielectric liner includes an inner liner layer and an outer liner layer.

Abstract: An imaging lens includes a light blocking sheet that includes an inner ring surface, a plurality of tapered light blocking structures, and a nanostructure layer. The inner ring surface surrounds an optical axis and defines a light passage opening. The tapered light blocking structures are disposed on the inner ring surface, and each tapered light blocking structure protrudes from the inner ring surface and tapers off towards the optical axis. The tapered light blocking structures are periodically arranged to surround the optical axis. The contour of each tapered light blocking structure has a curved part in a view along the optical axis. The curved part forms a curved surface on the inner ring surface. The nanostructure layer is disposed on the curved surface and has a plurality of ridge-like protrusions that extend non-directionally, and the average structure height of the nanostructure layer ranges from 98 nanometers to 350 nanometers.

Abstract: This disclosure provides systems, methods, and devices for wireless communication that support transmission of power limit indications for a UE associated with different frequency bands. In a first aspect, a method of wireless communication includes detecting a first trigger condition for transmission of at least a first indication of a first transmission power limit of the UE and a second indication of a second transmission power limit of the UE, wherein the first transmission power limit is associated with a first frequency band supported by the UE and the second transmission power limit is associated with a second frequency band supported by the UE and transmitting, to a first network node associated with the first frequency band, the first indication and the second indication in accordance with detection of the first trigger condition. Other aspects and features are also claimed and described.