Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.

Abstract: An equipment sensing circuit board and an operation method thereof are provided. The equipment sensing circuit board equipped on a semiconductor equipment includes a main sensor, a backup sensor, a first electronic fuse, a second electronic fuse, and a multiplexer. The main sensor and the backup sensor are used to monitor the operation of the semiconductor equipment to output a main sensing signal and a backup sensing signal respectively. The first electronic fuse is disposed on the main sensor to output a first status signal. The second electronic fuse is disposed on the backup sensor to output a second status signal. The multiplexer is connected to the main sensor, the backup sensor, the first electronic fuse and the second electronic fuse. The multiplexer selects to output the main sensing signal or the backup sensing signal according to the combination of the first state signal and the second state signal.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

Abstract: A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes a buried word line, a bit line, a bit line contact structure, a capacitive contact structure, and an air gap structure. The buried word line is formed in the substrate and extends along a first direction. The bit line is formed on the substrate and extends along a second direction. The bit line contact structure is formed below the bit line. The capacitive contact structure is adjacent to the bit line and surrounded by the air gap structure. The air gap structure includes a first air gap and a second air gap respectively located on a first side and a second side of the capacitive contact structure. The first air gap exposes a shallow trench isolation structure in the substrate. The second air gap exposes a top surface of the substrate.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.

Abstract: An electronic device and a method for screening features for predicting a physiological state are provided. The method includes: obtaining multiple physiological data corresponding to multiple features; generating multiple first subsets of the multiple features according to the multiple physiological data based on a first model, wherein the multiple first subsets respectively correspond to the multiple physiological data; selecting a first feature from the multiple features according to the multiple first subsets, calculating a first relation index of the first feature and a second feature corresponding to the multiple features, and selecting the second feature as an accompanied feature of the first feature according to the first relation index; and outputting the first feature and the accompanied feature.

Abstract: An electrical connection device is provided and includes a cable-end connector and a board-end connector. The cable-end connector includes an insulative housing and a circuit board. The insulative housing includes a housing body and a mating plate, the housing body has a front end face, the mating plate has a front end portion. The board-end connector includes an insulative base, a plurality of terminals and a metal outer shell. A mating groove is formed between the metal outer shell and the insulative base and is used to allow the mating plate to mate therewith. One of the insulative base and the metal outer shell is provided with a protruding member and when the cable-end connector reversely inserts into the board-end connector, the protruding member stops the front end portion of the mating plate.

Abstract: A memory device includes a substrate, an electrical channel layer, a first electrode, a resistive switching layer, a second electrode, and a conductive structure. The electrical channel layer is disposed on the substrate. The first electrode is disposed on the substrate and extends into the electrical channel layer. The resistive switching layer is disposed between the first electrode and the electrical channel layer. The second electrode is disposed on the electrical channel layer. The conductive structure connects the electrical channel layer and the second electrode.

Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.

Abstract: A semiconductor structure includes a substrate and a dielectric material disposed over the substrate. A void is disposed within the dielectric material. A dielectric liner is disposed along inner sidewalls of the dielectric material proximate to the void. An inner surface of the dielectric liner defines an outer extent of the void, and the dielectric liner includes an inner liner layer and an outer liner layer.

Abstract: A method for tuning an envelope tracking (ET) system includes: determining a setting combination from a plurality of setting available to the ET system, wherein determining the setting combination from the plurality of setting available to the ET system includes: determining, by a processing module, a first setting in a plurality of first settings included in the plurality of settings, and configuring the ET system by the first setting; and after the ET system is configured by the first setting, determining, by the processing module, a second setting in a plurality of second settings included in the plurality of settings, and configuring the ET system by the second setting. In addition, the setting combination includes the first setting and the second setting.

Abstract: Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure.

Abstract: An apparatus is disclosed for determining validity of a measured in-blood percentage of oxygenated hemoglobin. The apparatus has multiple pulse oximetry channels having at least three light sources of at least three distinct wavelengths, which are detected and converted to digital signals. The light sources are selectively activated, and two or more estimated in-blood percentages of oxygenated hemoglobin are calculated. It is determined whether a signal quality associated with the calculated in-blood percentages exceeds a predetermined accuracy threshold, and an associated validity indication is provided.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.

Abstract: A semiconductor device includes: a substrate, including an upper surface and a first to a fourth side surfaces; wherein the upper surface includes a first edge connecting the first side surface and a second edge opposite to the first edge and connecting the second side surface; a first modified trace formed on the first side surface; and a semiconductor stack formed on the upper surface, including a lower surface connecting the upper surface of the substrate, and the lower surface comprises a fifth edge adjacent to the first edge and a sixth edge opposite to the fifth edge and adjacent to the second edge; wherein a shortest distance between the first edge and the fifth edge is S1 ?m, and a shortest distance between the second edge and the sixth edge is S2 ?m; wherein in a lateral view viewing from the third side surface, the first side surface forms a first acute angle with a degree of ?1 with the vertical direction, the second side surface forms a second acute angle with a degree of ?2 with the vertical dire

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.

Abstract: A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a dielectric material disposed over the substrate and the gate structure, a conductive structure extending within the dielectric material, and a void extending within the dielectric material and disposed over the gate structure.

Abstract: A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed.