Abstract: In a method of manufacturing an attenuated phase shift mask, a photo resist pattern is formed over a mask blank. The mask blank includes a transparent substrate, an etch stop layer on the transparent substrate, a phase shift material layer on the etch stop layer, a hard mask layer on the phase shift material layer and an intermediate layer on the hard mask layer. The intermediate layer is patterned by using the photo resist pattern as an etching mask, the hard mask layer is patterned by using the patterned intermediate layer as an etching mask, and the phase shift material layer is patterned by using the patterned hard mask layer as an etching mask. The intermediate layer includes at least one of a transition metal, a transition metal alloy, or a silicon containing material, and the hard mask layer is made of a different material than the intermediate layer.

Abstract: A light path folding element includes a first surface, a second surface, a first reflecting surface and a second reflecting surface. A light travels from the first surface into the light path folding element. The second surface is disposed relative to the first surface along a first direction and is parallel to the first surface, and the first direction is perpendicular to the first surface. The first reflecting surface connects the first surface and the second surface, an acute angle is formed between the first reflecting surface and the first surface, and the light forms an internal reflection via the first reflecting surface. The light forms another internal reflection via the second reflecting surface. The light path folding element further includes a light blocking structure, which extends from at least one of the first surface and the second surface into the light path folding element.

Abstract: A buried gate structure and a method for forming the same are provided. The structure includes first and second gate dielectric layers respectively formed on the surface of the lower portion and the surface of the upper portion of a gate trench of the semiconductor substrate. The structure includes a first gate electrode formed on the first gate dielectric layer. The structure includes an insulating cap layer formed on the first gate electrode to fill the remaining space of the gate trench. The first gate dielectric layer includes a negative capacitance dielectric material. The second gate dielectric layer includes a different dielectric material than the negative capacitance dielectric material. The interface between the first gate dielectric layer and the second gate dielectric layer is lower than the bottom surfaces of the source region and the drain region of the semiconductor substrate.

Abstract: An optical device and the prism module thereof are provided. The prism module includes a first prism, a second prism, a film and a light guide unit. The film is disposed between the first prism and the second prism. First visible light enters the first prism, passes through the film, enters the second prism, exits from the second prism, reaches the light guide unit, and is reflected to user's eyes by the light guide unit. Also, second visible light passes through the light guide and reaches user's eyes.

Abstract: Described herein are genetic recognition reagents comprising terminal aromatic moieties that bind specifically to a template nucleic acid and concatenate. Also provided are methods of using the genetic recognition reagents, e.g., to treat or diagnose a repeat expansion disorder, such as DMI.

Abstract: A dispersion includes a zinc oxide component, and an aromatic polyol which is represented by Formula (I) and which has terminal hydroxyl groups that form chelating bonds with zinc atoms of the zinc oxide component, wherein p and q are independently integers ranging from 1 to 40. A method for preparing the dispersion includes heating a composition including the aromatic polyol and a zinc-containing salt, so that the zinc-containing salt undergoes nucleophilic reaction and condensation reaction to form the zinc oxide component. A composition for preparing the dispersion is also disclosed.

Abstract: An apparatus is disclosed for determining validity of a measured in-blood percentage of oxygenated hemoglobin. The apparatus has multiple pulse oximetry channels having at least three light sources of at least three distinct wavelengths, which are detected and converted to digital signals. The light sources are selectively activated, and two or more estimated in-blood percentages of oxygenated hemoglobin are calculated. It is determined whether a signal quality associated with the calculated in-blood percentages exceeds a predetermined accuracy threshold, and an associated validity indication is provided.

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

Abstract: System boot-up can be enabled in low temperature environments. A laptop or other battery-powered computing device can include multiple batteries and a battery architecture that allows the multiple batteries to simultaneously discharge to thereby provide adequate power to boot the system in low temperature environments. The battery architecture may also allow a battery with a higher relative state of charge to charge another battery with a lower relative state of charge to thereby equalize the batteries' relative states of charge.

Abstract: A method for tuning an envelope tracking (ET) system includes: determining a setting combination from a plurality of setting available to the ET system, wherein determining the setting combination from the plurality of setting available to the ET system includes: determining, by a processing module, a first setting in a plurality of first settings included in the plurality of settings, and configuring the ET system by the first setting; and after the ET system is configured by the first setting, determining, by the processing module, a second setting in a plurality of second settings included in the plurality of settings, and configuring the ET system by the second setting. In addition, the setting combination includes the first setting and the second setting.

Abstract: System boot-up can be enabled in low temperature environments. A laptop or other battery-powered computing device can include multiple batteries and a battery architecture that allows the multiple batteries to simultaneously discharge to thereby provide adequate power to boot the system in low temperature environments. The battery architecture may also allow a battery with a higher relative state of charge to charge another battery with a lower relative state of charge to thereby equalize the batteries' relative states of charge.

Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface. A semiconductor device is mounted on the top surface of the substrate. The semiconductor device has an active front surface directly facing the substrate, and an opposite rear surface. A vapor chamber lid is in thermal contact with the rear surface of the semiconductor device. The vapor chamber lid includes an internal vacuum-sealed cavity that stores a working fluid, and wick structures for recirculating the working fluid within the internal vacuum-sealed cavity.

Abstract: A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed.

Abstract: A method of generating a graphical user interface for horse race betting includes querying a database to obtain race data associated with a selected race, the race data including a list of horses scheduled to run the selected race, a track surface associated with the selected race, and a distance of the selected race. For each horse from among the list of horses, the method may include selecting a rating corresponding to the horse, the track surface, and the distance, the rating being selected from a plurality of ratings quantifying an expected performance of the horse for different combinations of track surface and distance and being derived from data associated with a sire and/or a dam of the horse. The method may include displaying the list of horses and displaying the selected ratings in association with the horses.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.

Abstract: A connector includes an insulative housing and a circuit board. The insulative housing comprises a housing body, an insertion plate, two side walls and a stopping wall. The housing body has a front end surface, the insertion plate is positioned at a top side of the housing body and protrudes from the front end surface, the two side walls are respectively positioned at a left side and a right side of the housing body and protrudes from the front end surface. The housing body, the insertion plate and the two side walls together form a receiving space. The stopping wall is positioned at a side of the insulating housing opposite to the insertion plate and has a stopping end positioned in front of the front end surface. The circuit board is provided to the housing body and partially protrudes into the receiving space. The stopping end of the stopping wall is stopped by the mating connector, it can prevent the user from improperly inserting the connector in an upside down orientation into the mating connector.

Abstract: A feature selection method is provided, including: inputting a plurality of pieces of training data into a plurality of training models to perform selection in a plurality of features through each training model for obtaining multiple feature pools; sorting the features based on the number of times each feature is selected by the feature pools to obtain a feature ranking; and extracting a plurality of designated features from the features based on the feature ranking.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

Abstract: An imaging lens includes a light blocking sheet that includes an inner ring surface, a plurality of tapered light blocking structures, and a nanostructure layer. The inner ring surface surrounds an optical axis and defines a light passage opening. The tapered light blocking structures are disposed on the inner ring surface, and each tapered light blocking structure protrudes from the inner ring surface and tapers off towards the optical axis. The tapered light blocking structures are periodically arranged to surround the optical axis. The contour of each tapered light blocking structure has a curved part in a view along the optical axis. The curved part forms a curved surface on the inner ring surface. The nanostructure layer is disposed on the curved surface and has a plurality of ridge-like protrusions that extend non-directionally, and the average structure height of the nanostructure layer ranges from 98 nanometers to 350 nanometers.