Patents by Inventor Wei-Cheng (Jason) Yu
Wei-Cheng (Jason) Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250217568Abstract: A layout method is provided. A timing analysis is performed based on design data of a standard cell to classify a plurality of device units of the standard cell into a timing-critical group and a non-timing-critical group. A plurality of first sources regions in the device units of the non-timing-critical group are aligned with a plurality of second sources regions in the device units of the timing-critical group in a first direction in floorplan of the standard cell in a layout. The device units of the timing-critical group are arranged in a first row of a cell array and the device units of the non-timing-critical group are arranged in a second row of the cell array. The first and second rows of the cell array share a common power line. First active regions of the first row are wider than second active regions of the second row.Type: ApplicationFiled: January 3, 2024Publication date: July 3, 2025Inventors: CHING-YU HUANG, WEI-CHENG LIN, JIANN-TYNG TZENG
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Publication number: 20250216534Abstract: An impact detection system includes processing circuitry with one or more processors. The impact detection system also includes memory storing instructions, that when executed by the processing circuitry, cause the processing circuitry to process positioning data to determine a position of a portable device within an interactive environment, compare the position of the portable device to a location of a boundary within the interactive environment, identify an occurrence of an impact event based on the position of the portable device and the location of the boundary, and update an impact profile for the portable device based on the occurrence of the impact event.Type: ApplicationFiled: December 20, 2024Publication date: July 3, 2025Inventors: Wei Cheng Yeh, Rachel Elise Rodgers
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Publication number: 20250216589Abstract: A display panel including a first substrate, a pixel-array layer, and a color-resist layer is disclosed. The pixel-array layer includes multiple first signal lines, multiple second signal lines, and multiple third signal lines. Each of the first signal lines corresponds to a common border between multiple first color resists and multiple second color resists. Each of the second signal lines corresponds to a common border between multiple third color resists and multiple first color resists. Each of the third signal lines corresponds to a common border between multiple second color resists and multiple third color resists. Reflected light coming from the first signal lines, reflected light coming from the second signal lines, and reflected light coming from the third signal lines are mixed to form white light.Type: ApplicationFiled: April 30, 2024Publication date: July 3, 2025Applicant: AUO CorporationInventors: Chia-Chun Hsu, Chen-Hao Chiang, Yu-Ping Kuo, Hsiao-Wei Cheng
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Publication number: 20250217638Abstract: Methods and systems for generating training data for training a contrastive language-audio machine-learning model. A plurality of audio segments are retrieved from a speech emotion recognition (SER) database along with metadata associated with the audio segments. The metadata of each audio segment includes an emotion class. Words or terms associated with emotions are retrieved from a lexicon. A large language model (LLM) is executed on (i) the classes of emotion associated with the audio segments and (ii) the words or terms from the lexicon. This generates a plurality of text captions associated with emotion, which are stored in a caption pool. For each audio segment retrieved from the SER database, that audio segment is paired with one or more of the text captions from the caption pool that were generated based on the emotion class associated with that audio segment. This yields audio-text pairs for training a contrastive learning model.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Inventors: Wei-Cheng Lin, Ho-Hsiang Wu, Shabnam Ghaffarzadegan, Luca Bondi, Abinaya Kumar, Samarjit Das
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Publication number: 20250218897Abstract: An integrated circuit includes frontside power rails in a frontside metal layer above the substrate, backside signal lines in a first backside metal layer below the substrate, backside power rails in a second backside metal layer below the first backside metal layer, and backside via-connectors passing through the substrate. A first frontside power rail and a first backside via-connector are conductively connected to the source terminal of a first-type transistor. A second frontside power rail and a second backside via-connector are conductively connected to the source terminal of a second-type transistor. A first extended via-connector is directly connected between the first backside via-connector and a first backside power rail. A second extended via-connector is directly connected between the second backside via-connector and a second backside power rail.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Inventors: Ching-Yu HUANG, Chun-Hsuang WANG, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG
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Publication number: 20250216633Abstract: An optical fiber connection base is provided, including a socket, a light emitting module, and an optical fiber bundle. The socket has an extension portion and a base having an accommodating space. The base is provided with an insertion hole and an alignment hole that are spatially communicated with each other. A first direction extends along the insertion hole. A side surface of the light emitting element of the light emitting module corresponds to the insertion hole, defining a light emitting surface. One end of the optical fiber bundle is inserted into the insertion hole in the first direction, such that a light receiving end is defined. The light receiving end is adjacent to the light emitting surface, and a center of a cross section of the light receiving end corresponds to a center of the light emitting surface.Type: ApplicationFiled: May 29, 2024Publication date: July 3, 2025Applicant: CLEVO CO.Inventors: Chien-Liang CHEN, Wei-Cheng LI, Hung-Chang HUANG
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Publication number: 20250218945Abstract: A device includes: a first cell region stacked on a second cell region; each including a first active region over a second active region; in a first layer of metallization (M_first layer) over the first active region, M_first power grid (PG) segments having a first reference voltage and M_first routing segments aligned correspondingly to M_first routing tracks; and in a first layer of metallization (BM_first layer) under the second active region, BM_first PG segments having a second reference, and BM_first routing segments aligned correspondingly to BM_first routing tracks. The M_first routing segments are aligned in the first and second cell regions correspondingly to first (Q1) and second (Q2) quantities of the M_first routing tracks, where Q2<Q1. The BM_first routing segments are aligned in the first and second cell regions correspondingly to third and fourth quantities of the BM_first routing tracks, where Q4<Q3.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Inventors: Chun-Yen LIN, Ching-Yu HUANG, Wei-Cheng LIN, Jiann-Tyng TZENG
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Publication number: 20250215240Abstract: A corrosion resistant structure is provided. The corrosion resistant structure includes a steel layer, a metal layer, and an organic layer. The metal layer contains zinc, aluminum, or a combination thereof. The metal layer is disposed on the steel layer. The metal layer is in contact with the steel layer. The metal layer and the steel layer have different compositions. The organic layer is disposed on the metal layer. The organic layer is in contact with the metal layer. The organic layer includes an organic resin, a diol compound containing two aliphatic rings, and an alkali earth metal salt.Type: ApplicationFiled: May 16, 2024Publication date: July 3, 2025Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hsiu-Pang YEH, Wei-Cheng TANG, Shu-Yun CHIEN, Hui-Chu HUANG
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Patent number: 12346815Abstract: A method for acquiring skills through imitation learning by employing a meta imitation learning framework with structured skill discovery (MILD) is presented. The method includes learning behaviors or tasks, by an agent, from demonstrations: by learning to decompose the demonstrations into segments, via a segmentation component, the segments corresponding to skills that are transferrable across different tasks, learning relationships between the skills that are transferrable across the different tasks, employing, via a graph generator, a graph neural network for learning implicit structures of the skills from the demonstrations to define structured skills, and generating policies from the structured skills to allow the agent to acquire the structured skills for application to one or more target tasks.Type: GrantFiled: October 11, 2023Date of Patent: July 1, 2025Assignee: NEC CorporationInventors: Wenchao Yu, Wei Cheng, Haifeng Chen, Yiwei Sun
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Patent number: 12346507Abstract: A stylus control circuit used to control a stylus includes a positioning signal generator. The positioning signal generator is used to generate a first positioning signal having a first frequency and transmit the first positioning signal to the stylus through a first positioning transmission electrode. Wherein, the first frequency corresponds to a position of the first positioning transmission electrode, and the first positioning signal is a frequency signal without carrying any digital data.Type: GrantFiled: January 18, 2023Date of Patent: July 1, 2025Assignee: NOVATEK Microelectronics Corp.Inventors: Hao-Wei Cheng, Chin-Lin Lee
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Patent number: 12346807Abstract: A method for acquiring skills through imitation learning by employing a meta imitation learning framework with structured skill discovery (MILD) is presented. The method includes learning behaviors or tasks, by an agent, from demonstrations: by learning to decompose the demonstrations into segments, via a segmentation component, the segments corresponding to skills that are transferrable across different tasks, learning relationships between the skills that are transferrable across the different tasks, employing, via a graph generator, a graph neural network for learning implicit structures of the skills from the demonstrations to define structured skills, and generating policies from the structured skills to allow the agent to acquire the structured skills for application to one or more target tasks.Type: GrantFiled: August 2, 2021Date of Patent: July 1, 2025Assignee: NEC CorporationInventors: Wenchao Yu, Wei Cheng, Haifeng Chen, Yiwei Sun
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Patent number: 12347772Abstract: A method of fabricating a semiconductor device is described. A semiconductor substrate having at least one electrical component is provided. A patterned wiring layer is formed above the semiconductor substrate. The patterned wiring layer includes a plurality of wiring portions, where adjacent of the wiring portions are separated from each other. A first insulating passivation layer is formed over the wiring portions in a region between adjacent wiring portions. The first insulating passivation layer has a horizontal surface in the region between adjacent wiring portions. A second insulating passivation layer is formed on the first insulating passivation layer, wherein the first insulating passivation layer has a side surface which makes an angle with the horizontal surface of greater than 103°.Type: GrantFiled: August 27, 2021Date of Patent: July 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuang-Wei Cheng, Chyi-Tsong Ni
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Patent number: 12349268Abstract: A package component includes a first substrate and a first conductive layer. The first substrate has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed over the first surface of the first substrate. The first conductive layer includes a first conductive feature and a second conductive feature over the first conductive feature. The second conductive features covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the second conductive feature. The first substrate includes a single-sided or a double-sided copper-clad laminate.Type: GrantFiled: January 25, 2024Date of Patent: July 1, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Wei Chang, Jian-Hong Lin, Shu-Yuan Ku, Wei-Cheng Liu, Yinlung Lu, Jun He
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Patent number: 12346814Abstract: A method for acquiring skills through imitation learning by employing a meta imitation learning framework with structured skill discovery (MILD) is presented. The method includes learning behaviors or tasks, by an agent, from demonstrations: by learning to decompose the demonstrations into segments, via a segmentation component, the segments corresponding to skills that are transferrable across different tasks, learning relationships between the skills that are transferrable across the different tasks, employing, via a graph generator, a graph neural network for learning implicit structures of the skills from the demonstrations to define structured skills, and generating policies from the structured skills to allow the agent to acquire the structured skills for application to one or more target tasks.Type: GrantFiled: October 11, 2023Date of Patent: July 1, 2025Assignee: NEC CorporationInventors: Wenchao Yu, Wei Cheng, Haifeng Chen, Yiwei Sun
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Publication number: 20250205387Abstract: The present disclosure relates to medical implant components comprising a biocompatible-bioactive composite material layer (BACL), methods of making the medical implant components and applications of the medical implant components.Type: ApplicationFiled: December 23, 2024Publication date: June 26, 2025Applicant: INNOJET TECHNOLOGY CO., LTD.Inventors: JEN-HSIEN CHANG, WEI-CHENG TANG, YANG-SHENG HUANG, YU-YEN TSAI
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Publication number: 20250212377Abstract: A stacked integrated circuit structure includes first and second semiconductor structures. The first semiconductor structure includes a first bit line, at least one first SRAM cell electrically connected with the first bit line, a first bonding metal layer, and at least one first vertical conductive structure connecting the first bit line to a first metal line of the first bonding metal layer. The second semiconductor structure is over and bonded with the first semiconductor structure. The second semiconductor structure includes a second bit line, at least one second SRAM cell electrically connected with the second bit line, a second bonding metal layer, and at least one second vertical conductive structure connecting the second bit line to a second metal line of the second bonding metal layer. The first metal line of the first bonding metal layer is bonded with the second metal line of the second bonding metal layer.Type: ApplicationFiled: December 21, 2023Publication date: June 26, 2025Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Rui-Teng CHANG, Tzu-Hsuan CHANG, Wei-Cheng KANG, Chang-Tsun SHIH, Han-Lun CHUANG, Jhen-Yu GUO, Liang-Chi HUANG, Ko-Cheng LU
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Publication number: 20250212510Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first conductivity type arranged in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second conductivity type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line arranged in a third layer between the first layer and the second layer. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate includes a recess portion, wherein the first conductive line is at an elevation of the recess portion.Type: ApplicationFiled: March 11, 2025Publication date: June 26, 2025Inventors: SHIH-WEI PENG, TE-HSIN CHIU, WEI-CHENG LIN, JIANN-TYNG TZENG
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Patent number: 12342647Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first photodiode in a substrate. The semiconductor arrangement includes a lens array over the substrate. A first plurality of lenses of the lens array overlies the first photodiode. Radiation incident upon the first plurality of lenses is directed by the first plurality of lenses to the first photodiode.Type: GrantFiled: February 22, 2021Date of Patent: June 24, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Feng-Chien Hsieh, Yun-Wei Cheng, Kuo-Cheng Lee
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Patent number: 12341098Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.Type: GrantFiled: September 1, 2021Date of Patent: June 24, 2025Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Wei-Cheng Lin
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Patent number: 12342736Abstract: An electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. The memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. The layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. The first material is a phase-change material and the second material is a non-phase-change material. The bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.Type: GrantFiled: December 8, 2022Date of Patent: June 24, 2025Assignee: International Business Machines CorporationInventors: Matthew Joseph BrightSky, Cheng-Wei Cheng, Guy M. Cohen, Robert L. Bruce, Asit Ray, Wanki Kim