Abstract: A method of forming an integrated circuit package includes following operations. A padding layer is formed on a portion of a carrier. A first semiconductor die is placed on the padding layer and a second semiconductor die is placed on the carrier. The first semiconductor die and the second semiconductor die are encapsulated with a first encapsulation layer. A first redistribution layer structure is formed over the first semiconductor die, the second semiconductor die and the first encapsulation layer. A third semiconductor die is placed on the first redistribution layer structure. The third semiconductor die is encapsulated with a second encapsulation layer. A second redistribution layer structure is formed over the third semiconductor die and the second encapsulation layer. The carrier is debonded. The padding layer is removed, and therefore, a recess is formed in the first encapsulation layer.

Abstract: The present disclosure relates integrated chip structure. The integrated chip structure includes one or more interconnects disposed within a dielectric structure over a substrate. A bond pad having a top surface is arranged along a top surface of the dielectric structure. The top surface of the bond pad includes a plurality of discrete top surface segments that are laterally separated from one another by non-zero distances that extend between interior sidewalls of the bond pad, as viewed in a cross-sectional view. The dielectric structure is disposed directly between the interior sidewalls of the bond pad.

Abstract: A circuit includes a first metal layer having a first first metal layer strip adjacent to a first boundary and a second first metal layer strip adjacent to a second boundary opposite to the first boundary. The first and second first metal layer strips, the first boundary, and the second boundary are parallel to each other. The circuit further includes a second metal layer having a first second metal layer strip and a second second metal layer strip adjacent to the first second metal layer strip. The first second metal layer strip is connected to the first metal layer strip at the first first metal layer strip and the second second metal layer strip is connected to the first metal layer strip at the second first metal layer strip. Each of the first and the second second metal layer strips are parallel to each other.

Abstract: An image sensor device is disclosed which includes a semiconductor layer having a first surface and a second surface, where the second surface is opposite to the first surface. The device includes a conductive structure disposed over the first surface, with a dielectric layer disposed between the conductive structure and the first surface. The device includes a first dielectric layer disposed over the second surface of the semiconductor substrate. The device includes a second dielectric layer disposed over the first dielectric layer. The device includes a color filter layer disposed over the second dielectric layer. In some embodiments, the thickness, refractive index, or both of the first dielectric layer and the thickness, refractive index, or both of the second dielectric layer may be collectively determined to cause incident radiation passing through the first dielectric layer and the second dielectric layer and to the plurality of pixels to have destructive interference.

Abstract: An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: A head-mounted display device and a control method for an eye-tracking operation are provided. The head-mounted display device includes a frame, a track, a sensor and a controller. The track is disposed on a peripheral region of the frame. The sensor is disposed on the track, and is configured to capture a target image of a target area. The controller is coupled to the sensor, is configured to generate a control signal according to the target image, and adjust a position of the sensor on the peripheral region by moving the sensor according to the control signal.

Abstract: The present disclosure relates to a semiconductor image sensor with improved quantum efficiency. The semiconductor image sensor can include a semiconductor layer having a first surface and a second surface opposite of the first surface. An interconnect structure is disposed on the first surface of the semiconductor layer, and radiation-sensing regions are formed in the semiconductor layer. The radiation-sensing regions are configured to sense radiation that enters the semiconductor layer from the second surface and groove structures are formed on the second surface of the semiconductor layer.

Abstract: Some implementations described herein provide pixel sensor configurations and methods of forming the same. In some implementations, one or more transistors of a pixel sensor are included on a circuitry die (e.g., an application specific integrated circuit (ASIC) die or another type of circuitry die) of an image sensor device. The one or more transistors may include a source follower transistor, a row select transistor, and/or another transistor that is used to control the operation of the pixel sensor. Including the one or more transistors of the pixel sensor (and other pixel sensors of the image sensor device) on the circuitry die reduces the area occupied by transistors in the pixel sensor on the sensor die. This enables the area for photon collection in the pixel sensor to be increased.

Abstract: A pixel sensor includes a photodiode including an anode overlying a cathode positioned in a substrate and a transfer transistor structure including a source region extending along a surface of the substrate adjacent to the anode and overlying the cathode, a floating diffusion region extending along the surface of the substrate parallel to the source region, and a gate conductor including an array of conductive protrusions extending into the substrate between the source region and the floating diffusion region.

Abstract: A polymer and a coating material are provided. The polymer is formed by polymerizing a plurality of monomers. The monomers include a first monomer, a second monomer, and a third monomer. The first monomer is itaconic acid. The second monomer is C1-4 alkyl methacrylate, styrene, isobornyl acrylate, di(C2-4 alkyl) itaconate, or a combination thereof. The third monomer is 2-octylacrylate, C9-12 alkyl acrylate, or a combination thereof. The coating material includes the polymer.

Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

Abstract: A multi-platform live streaming device is provided. The multi-platform live streaming device includes: a user interface service module and a streaming output service module. The user interface service module is configured to control one or more image elements based on a user interface setting, thereby determining screen layouts of a local monitoring video and a live output video respectively. The streaming output service module is configured to encode the live output video to generate live streaming media and streaming the live streaming media simultaneously to multiple live streaming platforms. Specifically, the screen layout of the local monitoring video can differ from that of the live output video.

Abstract: A system for enhancing animation media production that yields animated media or scenes that seamlessly blend with real-world environments. The system comprises a computing device having at least one processor and a memory in communication with the processor configured to store instructions that are executable by the processor. The computing device is in communication with a server through a network. The system uses neural radiance field (NeRF) system to provide depth maps. The system uses simultaneous localization and mapping system to monitor and map the environment in a 3D model of a scene in real-time environments. The system uses distributed AI agents, which ensures animated characters and elements can instantly adapt to dynamic changes in the environment, thereby eliminating post-production corrections when unexpected changes occur during filming. The system computes accurate lighting conditions and perspectives of the animated elements.

Abstract: A display device includes a display module and a decorative layer. The display module includes sub-pixels, and a line connecting the midpoints of any two opposite sides of each sub-pixel forms an auxiliary center line. The decorative layer has a through hole and is arranged above the display module. Each sub-pixel corresponds to n through holes, and n is a positive integer. When n is 1, the through hole is located within the coverage of the sub-pixel, and a first top view area of the sub-pixel is 1.5 times to 6 times a second top view area of the through hole. Or the sub-pixel is located within the coverage of the through hole, and the second top view area of the through hole is 1.5 times to 6 times the first top view area of the sub-pixel.

Abstract: A device includes a plurality of photodiode regions within a semiconductor substrate, a plurality of transistors over a front-side surface of the semiconductor substrate, a plurality of deep trench isolation (DTI) structures extending a first depth from a backside surface of the semiconductor substrate into the semiconductor substrate, and a plurality of isolation structures extending a second depth from the backside surface of the semiconductor substrate into the semiconductor substrate. The second depth is less than the first depth. One of the plurality of isolation structures has a quadrilateral outline on the backside surface of the semiconductor substrate. The isolation structure includes two triangular surfaces and two rectangular surfaces respectively extending from four sides of the quadrilateral outline.

Abstract: A method includes fabricating a first-voltage underlayer power rail conductively connecting to the source region of a first-type transistor and fabricating a second-voltage underlayer power rail conductively connecting to the source region of a second-type transistor. Each of the first-voltage and second-voltage underlayer power rails extends in a first direction. The method also includes patterning a first connection layer to form a first-voltage power rail and a second-voltage power rail extending in the second direction which is perpendicular to the first direction. The first-voltage power rail is directly connected with the first-voltage underlayer power rail through a first via-connector and the second-voltage power rail is directly connected with the second-voltage underlayer power rail through a second via-connector.

Abstract: A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

Abstract: Apparatus and methods for back side routing a data signal in a semiconductor device are described. In one example, a described semiconductor cell structure includes: a dummy device region at a front side of the semiconductor cell structure; a metal layer including a plurality of metal lines at a back side of the semiconductor cell structure; a dielectric layer formed between the dummy device region and the metal layer; an inner metal disposed within the dielectric layer; at least one first via that is formed through the dielectric layer and electrically connects the inner metal to the plurality of metal lines at the back side; and at least one second via that is formed in the dielectric layer and physically coupled between the inner metal and the dummy device region at the front side.

Abstract: A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.