Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

Abstract: A Multi-Access Edge Computing (MEC) system is provided. The MEC system includes a user equipment (UE), an MEC device, and a core network. The MEC device includes a relay User Plane Function (UPF) module, a first UPF module, and a second UPF module. The core network performs a UPF path management corresponding to the UE based on a notification of the MEC device. When the UE attaches to a network, the MEC device establishes an idle session between the UE and the relay UPF module. When the MEC device determines that a service for the UE needs to be switched from the first UPF module to the second UPF module and the second UPF module has not been activated, the MEC device notifies the core network to switch the service for the UE from the first UPF module to the relay UPF module first.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.

Abstract: An optical driving mechanism is provided, for driving an optical element, including: a fixed portion, a movable portion, a driving assembly and a position sensing assembly. The movable portion is movably connected to the fixed portion and includes a holder for sustaining the optical element. The driving assembly is configured to drive the movable portion to move relative to the fixed portion. The position sensing assembly is configured to sense a distance of the movable portion relative to the fixed portion, the position sensing assembly includes a sensing magnetic element and a sensor, wherein the sensing magnetic element is disposed on the movable portion and has a rectangular structure. A direction of a long axis of the rectangular structure extends in a direction that is perpendicular to the optical axis of the optical element, and the direction of the long axis is different from the optical axis direction.

Abstract: A method according to the present disclosure includes providing a substrate that includes a dummy gate stack wrapping over an active region, and a spacer layer extending along sidewalls of the dummy gate stack, selectively removing the dummy gate stack to form a gate trench exposing the active region, depositing a gate dielectric over the active region, depositing at least one work function layer over the gate dielectric layer, depositing a tungsten layer over the at least one work function layer, and depositing a tungsten nitride layer over the tungsten layer.

Abstract: A Multi-Access Edge Computing (MEC) system is provided. The MEC system includes a user equipment (UE), an MEC device, and a core network. The MEC device includes a relay User Plane Function (UPF) module, a first UPF module, and a second UPF module. The core network performs a UPF path management corresponding to the UE based on a notification of the MEC device. When the UE attaches to a network, the MEC device establishes an idle session between the UE and the relay UPF module. When the MEC device determines that a service for the UE needs to be switched from the first UPF module to the second UPF module and the second UPF module has not been activated, the MEC device notifies the core network to switch the service for the UE from the first UPF module to the relay UPF module first.

Abstract: A method and a system for switching multi-function modes applied in an electronic device having a plurality of hardware module functions, and includes receiving input information from a user of the electronic device; obtaining status information of the electronic device; and switching the electronic device to one of the multi-function modes according to the input information and the status information, each of the multi-function modes corresponds to at least one of the plurality of hardware module functions.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.

Abstract: Embodiments provide a replacement metal gate in a FinFET or nanoFET which utilizes a conductive metal fill. The conductive metal fill has an upper surface which has a fin shape which may be used for a self-aligned contact.

Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.

Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

Abstract: A semiconductor device includes an active region. A metal gate electrode is disposed over the active region. A conductive layer is disposed over the metal gate electrode. A silicon-containing layer is disposed over a first portion of the conductive layer. A dielectric layer is disposed over a second portion of the conductive layer. A gate via vertically extends through the silicon-containing layer. The gate via is disposed over, and electrically coupled to, the metal gate electrode.