Abstract: The present invention discloses an RF element group testing system and method. The method comprises steps: adding an identification feature to a first RF signal, which is output by one of the plurality of tested RF elements, to generate an identification RF signal; synthesizing the identification RF signal and a second RF signal, which is output by each of the rest of the tested RF elements, to generate a corresponding synthesis signal; resolving the synthesis signal into the identification RF signal and the corresponding second RF signal according to the identification feature; restoring the identification RF signal into the first RF signal; and calculating at least one signal-feature parameter of the first RF signal and the second RF signal.

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

Abstract: In an automatic gamma adjustment system with environmental adaptability, the system is installed in a display device and an image signal source is selected, such that an image signal is received and converted into first YUV signals, while detecting the surrounding situation to obtain at least one environmental data, and obtaining a gamma control parameter of a display screen of the display device according to the environmental data. When the environmental data is calculated to obtain a maximum brightness current value, the gamma control parameter is used to calculate the first YUV signals as second YUV signals, and the maximum brightness current value and the second YUV signals are sent to the display device for displaying the image. Therefore the grayscale layering effect of an image presented to people can be adjusted by automatically correcting the gamma value according to the surrounding situation at any time.

Abstract: Three dimensional object reconstruction for sensor simulation includes performing operations that include rendering, by a differential rendering engine, an object image from a target object model, and computing, by a loss function of the differential rendering engine, a loss based on a comparison of the object image with an actual image and a comparison of the target object model with a corresponding lidar point cloud. The operations further include updating the target object model by the differential rendering engine according to the loss, and rendering, after updating the target object model, a target object in a virtual world using the target object model.

Abstract: A method for manufacturing a semiconductor device to which corresponds a layout diagram stored on a non-transitory computer-readable medium. The method includes generating the layout diagram using an electronic design system (EDS), the EDS including at least one processor and at least one memory including computer program code for one or more programs are configured to cause the EDS to execute the generating. Testing the semiconductor device. Revising, the layout diagram, based on testing results indicative of selected standard functional cells in the layout diagram which merit modification or replacement. Programming one or more of the ECO cells which correspond to the one or more selected standard functional cells resulting in one or more programmed ECO cells. Routing the one or more programmed ECO cells correspondingly to at least one of the selected standard functional cells or to one or more other ones of the standard functional cells.

Abstract: An acoustic block manufacturing method includes: mixing zeolite powder with water to form a mixed liquid; making the mixed liquid into an ice cube; providing a vacuum environment to make the ice cube undergo gas phase sublimation; and feeding parylene into the vacuum environment in a manner of chemical vapor deposition to form an acoustic block having a porous structure. The acoustic block can effectively reduce resonance frequency. An acoustic device with acoustic blocks is also provided and has the same effect.

Abstract: A display panel includes a pixel unit. The pixel unit includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first light-emitting element, a first light source element, and a first color conversion structure. A light emitted by the first light-emitting element has a first color. The first color conversion structure is disposed on the first light source element and adapted to convert a light emitted by the first light source element into a light of the first color. The second sub-pixel includes a second light-emitting element. A light emitted by the second light-emitting element has a second color different from the first color.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

Abstract: The present disclosure describes a method for forming a silicon-based, carbon-rich, low-k ILD layer with a carbon concentration between about 15 atomic % and about 20 atomic %. For example, the method includes depositing a dielectric layer, over a substrate, with a dielectric material having a dielectric constant below 3.9 and a carbon atomic concentration between about 15% and about 20%; exposing the dielectric layer to a thermal process configured to outgas the dielectric material; etching the dielectric layer to form openings; and filling the openings with a conductive material to form conductive structures.

Abstract: A method of handling a workpiece includes the following steps. A workpiece is placed on a chuck body, wherein the workpiece includes a tape carrier extending beyond a periphery of the chuck body and a workpiece body disposed on the tape carrier, and the chuck body includes a seal ring surrounding the periphery of the chuck body; the tape carrier is clamped outside the chuck body, wherein the tape carrier leans against the seal ring and an enclosed space is formed between the chuck body, the tape carrier and the seal ring; and a vacuum seal is formed by evacuating gas from the enclosed space to pull the periphery of the workpiece toward the chuck body.

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

Abstract: The present disclosure provides systems and methods that combine physics-based systems with machine learning to generate synthetic LiDAR data that accurately mimics a real-world LiDAR sensor system. In particular, aspects of the present disclosure combine physics-based rendering with machine-learned models such as deep neural networks to simulate both the geometry and intensity of the LiDAR sensor. As one example, a physics-based ray casting approach can be used on a three-dimensional map of an environment to generate an initial three-dimensional point cloud that mimics LiDAR data. According to an aspect of the present disclosure, a machine-learned geometry model can predict one or more adjusted depths for one or more of the points in the initial three-dimensional point cloud, thereby generating an adjusted three-dimensional point cloud which more realistically simulates real-world LiDAR data.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

Abstract: An ultrasonic welding device includes a first component and a second component. The first component includes at least one first welding feature and at least one second welding feature which are arranged along a horizontal direction, and the first and second welding features have different sizes in a vertical direction. The second component has at least one welding structure which is configured to be in contact with the first and second welding features, so as to weld the first and second components.

Abstract: An electrical device includes a container, a conversion unit, an outer cover and an inner cover. The container is provided with an inner bottom surface and an inner which define an accommodating channel together. An inlet of the accommodating channel is opposite to the inner bottom surface. The conversion unit is disposed within the accommodating channel. The outer cover covers the inlet of the accommodating channel. The inner cover is disposed within the accommodating channel, and located between the conversion unit and the outer cover. One part of the conversion unit extends to the opening, and at least one outer edge of the inner cover is connected to an inner wall of the container.

Abstract: An electronic device is provided, which includes a first body, a second body, and a pivot structure connecting the first body and the second body. The pivot structure includes a shaft with an axis, a first assembling element assembled with the shaft and connected with the first body and a second assembling element pivotally connected to the shaft and connected with the second body. The second assembling element includes an abutting portion. When at the first position, the abutting portion and the first assembling element are located on the same side relative to the axis. When at the second position, the abutting portion rotates around the axis and is located on a different side relative to the axis, and the abutting portion abuts the abutting surface to generate an abutting force. Then the first body rises and an angle relative to the abutting surface is generated.