Abstract: A guidance unit comprises a first pipe part and a second pipe part, an inner space diameter of the second pipe part is smaller than an inner space diameter of the first pipe part, causing a cross-sectional area of a second flow space perpendicular to a pipe axis of the second pipe part smaller than that of a first flow space perpendicular to a pipe axis of the first pipe part; one end of the pipe axis of the second pipe part and one end of the pipe axis of the first pipe part are connected in series with each other and spaced apart from each other by a first angle, so that the second flow space communicates with the first flow space; thereby, a pressure of an external fluid in the second flow space is greater than a pressure of the external fluid in the first flow space.

Abstract: A micro light-emitting diode display device includes a display substrate, multiple pixels, and at least one color conversion layer. The pixels are disposed on the display substrate. Each of the pixels includes multiple sub-pixels. Each of the sub-pixels includes at least one micro light-emitting diode. The at least one color conversion layer is disposed on the pixels. The at least one color conversion layer is continuously disposed on at least a part of sub-pixels of different pixels along a same direction.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

Abstract: A triadic recurve implosion flood navigation for in-situ tailoring yearn system -[TRINITY - D20] has a tailoring mechanism comprising a first unit having an arc-shaped first arcuate portion, and a second unit having an arc-shaped second arcuate portion, the first and second units stagger each other with concave arcuate surfaces facing opposite directions by center axes of curvature of the first and second arcuate portions parallelling each other to cause an arcuate end of the first arcuate portion locate between two arcuate ends of the second arcuate portion and separated from the concave arcuate surface of the second arcuate portion by a first distance, and to cause an arcuate end of the second arcuate portion locate between two arcuate ends of the first arcuate portion and separated from the first arcuate portion by a second distance, thereby the first and second arcuate portions jointly define a curved channel.

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

Abstract: A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

Abstract: A backlight module includes a light guide plate and a plurality of light-emitting elements. The light guide plate includes a light-incident surface, an effective light-exiting region, a transition region located between the light-incident surface and the effective light-exiting region, and a light-blocking opening disposed in the transition region. The light-emitting elements are disposed at the light-incident surface and emit light toward the effective light-exiting region. The light-blocking opening is located between a plurality of light-emitting regions formed in the transition region by the plurality of light-emitting elements respectively.

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.

Abstract: Various noise isolation structures and methods for fabricating the same are presented. In one example, a substrate for chip package is provided. The substrate includes a core region, top build-up layers and bottom build-up layers. The top build-up layers are formed on a first side of the core region and the bottom build-up layers are formed on a second side of the core region that is opposite the first side. Routing circuitry formed in the bottom build-up layers is coupled to routing circuitry formed in the top build-up layers by vias formed through the core region. A void is formed in the bottom build-up layers. The void is configured as a noise isolation structure. The void has a sectional area that is different in at least two different distances from the core region.

Abstract: Systems and methods are provided for machine-learned models including convolutional neural networks that generate predictions using continuous convolution techniques. For example, the systems and methods of the present disclosure can be included in or otherwise leveraged by an autonomous vehicle. In one example, a computing system can perform, with a machine-learned convolutional neural network, one or more convolutions over input data using a continuous filter relative to a support domain associated with the input data, and receive a prediction from the machine-learned convolutional neural network. A machine-learned convolutional neural network in some examples includes at least one continuous convolution layer configured to perform convolutions over input data with a parametric continuous kernel.

Abstract: A device may include a first package and a second package where the first package has a warped shape. First connectors attached to a redistribution structure of the first package include a spacer embedded therein. Second connectors attached to the redistribution structure are fee from the spacer, the spacer of the first connectors keeping a minimum distance between the first package and the second package during attaching the first package to the second package.

Abstract: A device for testing a group of radio-frequency (RF) chip modules and a method for using the same is disclosed. The device includes a signal analyzer, a power divider, control ICs, a signal controller, and a power combiner. The power divider receives an RF signal and transmits RF input signals to the RF chip modules and the control ICs in response to the RF signal. The signal controller controls each control IC to adjust at least one of the power and the phase of the corresponding RF input signal, thereby generating an RF output signal. The power combiner receives the RF output signal from each control IC to generate a test signal. The signal analyzer receives the test signal and obtains RF properties corresponding to at least one of the power and the phase of each RF output signal.

Abstract: A system for testing antenna-in-package (AiP) modules and a method for using the same is disclosed. Firstly, AiP modules respectively receive RF signals from a testing transmitting antenna. Then, at least one of the power and the phase of each of the RF signals is adjusted to generate modulated RF amplified signals as recognition tags with difference. The RF amplified signals are received from each control integrated circuit (IC) and the power of the modulated RF amplified signals is summed to generate a net mixed test signal. Finally, the test signal is received and RF properties corresponding to at least one of the power and the phase of each of the RF amplified signals as recognition tags are obtained. The method can simultaneously test a plurality of AiP modules to shorten the test time.

Abstract: A semiconductor device includes first and second fin active regions extruding from a substrate, where the first and second fin active regions are separated by an isolation feature. The semiconductor includes a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region. The semiconductor device includes first source/drain features formed on the first fin active region, second source/drain features formed on the second fin active region, and a dielectric layer disposed along sidewalls of the first fin active region but not along sidewalls of the second fin active region. The first source/drain features extend vertically into the first fin active region at a first depth, the second source/drain features extend vertically into the second fin active region at a second depth, and the first depth is greater than the second depth.

Abstract: An antenna measurement system is configured to measure a radiation field pattern of an AUT fixed on a reference surface. The antenna measurement system includes an articulated robot, a measurement component, and a processor. The articulated robot is seated on a periphery of the reference surface, with a movable end capable of scanning a short-distance area defined by the reference surface. The measurement component is arranged on the movable end of the articulated robot, and a front surface of the measurement component is a specific geometric surface, which is used to face the antenna for radiation measurement. The processor is coupled to the movable end to control the movable end to drive the measurement component to move relative to the antenna along a predefined scanning path, and keep the specific geometric surface facing the antenna during the movement along the scanning path.

Abstract: A micro LED display device includes: a substrate; a plurality of micro light-emitting diodes disposed on the substrate; and a reflective layer and a black layer sequentially stacked on the substrate. The reflective layer and the black layer cover a surface of the substrate, wherein a top surface of the plurality of micro light-emitting diodes is exposed through the reflective layer and the black layer. A plurality of reflective banks and a plurality of black banks are sequentially disposed on the black layer and exposing the plurality of micro light-emitting diodes; and a color-conversion material covers the top surface of at least one of the plurality of micro light-emitting diodes. The color-conversion material is laterally disposed between the plurality of reflective banks. The reflective layer, the black layer, the plurality of reflective banks, and the plurality of black banks overlap each other in a display direction.

Abstract: Generally, the disclosed systems and methods implement improved detection of objects in three-dimensional (3D) space. More particularly, an improved 3D object detection system can exploit continuous fusion of multiple sensors and/or integrated geographic prior map data to enhance effectiveness and robustness of object detection in applications such as autonomous driving. In some implementations, geographic prior data (e.g., geometric ground and/or semantic road features) can be exploited to enhance three-dimensional object detection for autonomous vehicle applications. In some implementations, object detection systems and methods can be improved based on dynamic utilization of multiple sensor modalities. More particularly, an improved 3D object detection system can exploit both LIDAR systems and cameras to perform very accurate localization of objects within three-dimensional space relative to an autonomous vehicle.

Abstract: An exposure apparatus including a micro light emitting diode display unit and a first projection optical system is provided. The micro light emitting diode display unit has a plurality of micro light emitting diodes. The micro light emitting diode display unit is adapted to individually control light emission signals of the micro light emitting diodes and forming a predetermined pattern. The first projection optical system is disposed on a light emitting path of the micro light emitting diode display unit. The first projection optical system is configured to form an exposure pattern on a photosensitive material layer at once by applying the predetermined pattern.

Abstract: A dual band antenna and an electronic device are provided. The dual band antenna includes a feed end, an annular connection end, a metal screw, a first extension path, a second extension path, a third extension path, and a grounding part. The annular connection end has an opening and is connected to the feed end. The metal screw has a threaded stud passing through the opening, so that the metal screw is electrically connected to the annular connection end. The feed end, the first extension path, the second extension path, the third extension path, and the grounding part are sequentially connected to each other. The dual band antenna is configured to have a monopole antenna and a loop antenna, so that the dual band antenna has a wide operating frequency band, and the monopole antenna operates at 3.6 GHz and the loop antenna operates at 4.6 GHz.

Abstract: A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.