Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.

Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.

Abstract: Compute engine circuitry configured to represent a spin network mapping of a graph representing a combinatorial optimization problem includes a plurality of ring oscillator cells, each of which includes a ring oscillator having an oscillator output, at least one coupling block, and a read block. Each coupling block connects the ring oscillator of the cell to the ring oscillator of one of a plurality of neighboring cells to form a coupled ring oscillator. The read block generates a state output for each coupled ring oscillator that indicates whether the coupled ring oscillator is in one of a same-phase state, in which the connected ring oscillators oscillate in phase with each other, and an opposite-phase state, in which the connected ring oscillators oscillate in an opposite phase from each other. A controller is configured to output a total energy of the mapping based on the state outputs.

Abstract: A triadic recurve implosion flood navigation for in-situ tailoring yearn system—[TRINITY-D20] has a tailoring mechanism comprising a first unit having an arc-shaped first arcuate portion, and a second unit having an arc-shaped second arcuate portion, the first and second units stagger each other with concave arcuate surfaces facing opposite directions by center axes of curvature of the first and second arcuate portions parallelling each other to cause an arcuate end of the first arcuate portion locate between two arcuate ends of the second arcuate portion and separated from the concave arcuate surface of the second arcuate portion by a first distance, and to cause an arcuate end of the second arcuate portion locate between two arcuate ends of the first arcuate portion and separated from the first arcuate portion by a second distance, thereby the first and second arcuate portions jointly define a curved channel.

Abstract: A slurry blending tool may include a blending tank to receive and blend one or more materials into a slurry, and at least one inlet pipe connected to the blending tank and to provide the one or more materials to the blending tank. The at least one inlet pipe may vertically enter the blending tank and may not contact the blending tank. The slurry blending tool may include a blending pump partially provided within the blending tank and to blend the one or more materials into the slurry. The slurry blending tool may include an outlet pipe connected to the blending pump and to remove the slurry from the blending tank.

Abstract: The present disclosure provides systems and methods that combine physics-based systems with machine learning to generate synthetic LiDAR data that accurately mimics a real-world LiDAR sensor system. In particular, aspects of the present disclosure combine physics-based rendering with machine-learned models such as deep neural networks to simulate both the geometry and intensity of the LiDAR sensor. As one example, a physics-based ray casting approach can be used on a three-dimensional map of an environment to generate an initial three-dimensional point cloud that mimics LiDAR data. According to an aspect of the present disclosure, a machine-learned model can predict one or more dropout probabilities for one or more of the points in the initial three-dimensional point cloud, thereby generating an adjusted three-dimensional point cloud which more realistically simulates real-world LiDAR data.

Abstract: A continuous memory access acceleration circuit, an address shift circuit, and an address generation method are provided. An arithmetic circuit calculates a memory access address according to temporary data provided by a register circuit. A counter provides a count value. A counting control circuit controls the counter to accumulate the count value according to access times of a memory. An adder circuit adds the memory access address and the count value to generate a target memory access address.

Abstract: The present invention discloses an RF element group testing system and method. The method comprises steps: adding an identification feature to a first RF signal, which is output by one of the plurality of tested RF elements, to generate an identification RF signal; synthesizing the identification RF signal and a second RF signal, which is output by each of the rest of the tested RF elements, to generate a corresponding synthesis signal; resolving the synthesis signal into the identification RF signal and the corresponding second RF signal according to the identification feature; restoring the identification RF signal into the first RF signal; and calculating at least one signal-feature parameter of the first RF signal and the second RF signal.

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

Abstract: In an automatic gamma adjustment system with environmental adaptability, the system is installed in a display device and an image signal source is selected, such that an image signal is received and converted into first YUV signals, while detecting the surrounding situation to obtain at least one environmental data, and obtaining a gamma control parameter of a display screen of the display device according to the environmental data. When the environmental data is calculated to obtain a maximum brightness current value, the gamma control parameter is used to calculate the first YUV signals as second YUV signals, and the maximum brightness current value and the second YUV signals are sent to the display device for displaying the image. Therefore the grayscale layering effect of an image presented to people can be adjusted by automatically correcting the gamma value according to the surrounding situation at any time.

Abstract: Three dimensional object reconstruction for sensor simulation includes performing operations that include rendering, by a differential rendering engine, an object image from a target object model, and computing, by a loss function of the differential rendering engine, a loss based on a comparison of the object image with an actual image and a comparison of the target object model with a corresponding lidar point cloud. The operations further include updating the target object model by the differential rendering engine according to the loss, and rendering, after updating the target object model, a target object in a virtual world using the target object model.

Abstract: A method for manufacturing a semiconductor device to which corresponds a layout diagram stored on a non-transitory computer-readable medium. The method includes generating the layout diagram using an electronic design system (EDS), the EDS including at least one processor and at least one memory including computer program code for one or more programs are configured to cause the EDS to execute the generating. Testing the semiconductor device. Revising, the layout diagram, based on testing results indicative of selected standard functional cells in the layout diagram which merit modification or replacement. Programming one or more of the ECO cells which correspond to the one or more selected standard functional cells resulting in one or more programmed ECO cells. Routing the one or more programmed ECO cells correspondingly to at least one of the selected standard functional cells or to one or more other ones of the standard functional cells.

Abstract: An acoustic block manufacturing method includes: mixing zeolite powder with water to form a mixed liquid; making the mixed liquid into an ice cube; providing a vacuum environment to make the ice cube undergo gas phase sublimation; and feeding parylene into the vacuum environment in a manner of chemical vapor deposition to form an acoustic block having a porous structure. The acoustic block can effectively reduce resonance frequency. An acoustic device with acoustic blocks is also provided and has the same effect.

Abstract: A display panel includes a pixel unit. The pixel unit includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first light-emitting element, a first light source element, and a first color conversion structure. A light emitted by the first light-emitting element has a first color. The first color conversion structure is disposed on the first light source element and adapted to convert a light emitted by the first light source element into a light of the first color. The second sub-pixel includes a second light-emitting element. A light emitted by the second light-emitting element has a second color different from the first color.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

Abstract: The present disclosure describes a method for forming a silicon-based, carbon-rich, low-k ILD layer with a carbon concentration between about 15 atomic % and about 20 atomic %. For example, the method includes depositing a dielectric layer, over a substrate, with a dielectric material having a dielectric constant below 3.9 and a carbon atomic concentration between about 15% and about 20%; exposing the dielectric layer to a thermal process configured to outgas the dielectric material; etching the dielectric layer to form openings; and filling the openings with a conductive material to form conductive structures.