Abstract: A cavity interposer has a cavity, first bondpads adapted to couple to a chip-type camera cube disposed within a base of the cavity at a first level, the first bondpads coupled through feedthroughs to second bondpads at a base of the interposer at a second level; and third bondpads adapted to couple to a light-emitting diode (LED), the third bondpads at a third level. The third bondpads coupled to fourth bondpads at the base of the interposer at the second level; and the second and fourth bondpads couple to conductors of a cable with the first, second, and third level different. An endoscope optical includes the cavity interposer an LED, and a chip-type camera cube electrically bonded to the first bondpads; the LED is bonded to the third bondpads; and a top of the chip-type camera cube and a top of the LED are at a same level.

Abstract: A method of image sensor package fabrication includes forming a recess in a transparent substrate, depositing conductive traces in the recess, inserting an image sensor in the recess so that the image sensor is positioned in the recess to receive light through the transparent substrate, and inserting a circuit board in the recess so that the image sensor is positioned between the transparent substrate and the circuit board.

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

Abstract: A method and system for identifying a gum line of a tooth model, a device, and a storage medium are disclosed. The method includes:extracting a plurality of feature points from the tooth model based on a curvature algorithm, pre-processing each of the feature points, and outputting a contour point group (S1); obtaining a target reference line from a pre-stored reference line pool withthe target reference line being matched witha shape parameter of the tooth model (S2); fitting the target reference line based on the contour point group by iterative operation, to generate a fitting reference line (S3); and performing smoothing processing on the fitting reference line by using a dimensionality reduction algorithm, to output the gum line (S4).

Abstract: The present disclosure discloses a shift register unit and a threshold voltage compensation method thereof, a driving circuit and a display apparatus. The shift register unit includes a cascaded output circuit coupled to a pull-up node, a clock signal input terminal, and a cascaded signal output terminal. The shift register unit is configured to transmit a clock signal from the clock signal input terminal to the cascaded signal output terminal under control of the pull-up node. A compensation circuit has a voltage output terminal coupled to the pull-up node, and is configured to provide an output voltage signal through the voltage output terminal during a blanking phase of a frame. The output voltage signal drives reverse drift of a threshold voltage of the cascaded output circuit.

Abstract: An electrical connector includes an insulative housing having a mating slot; a contact module received in the insulative housing, a metallic outer shell enclosing the insulative housing and having a latching portion spaced apart from a side wall of the insulative housing, and a metallic inner shield secured between the insulative housing and the metallic outer shell, wherein the metallic inner shield has a planar portion adjacent to the side wall of the insulative housing and a pair of bulging portions at two opposite ends of the planar portion, and the latching portion of the metallic outer shell and the planar portion and the bulging portions of the metallic inner shield together define an engaging groove.

Abstract: The present disclosure provides a package structure, an antenna module, and a probe card. The package structure includes a connection member and a first redistribution structure disposed on the connection member. The connection member includes a conductive connector and an insulation layer surrounding the conductive connector. The first redistribution structure includes a first dielectric layer, and a first wiring pattern, and a first device. The first dielectric layer is disposed on the connection member. The first wiring pattern is disposed in the first dielectric layer. The first device is disposed above the first dielectric layer and is electrically connected to the conductive connector.

Abstract: An image sensor module comprises an image sensor having a light sensing area, a cover glass for covering the light sensing area, a dam between the image sensor and the cover glass, which surrounds the light sensing area, and has an outer wall and an inner wall, where a cross-section of the inner wall parallel to the surface of the light sensing area of the image sensor forms a sawtooth pattern and/or, where a cross-section of the inner wall orthogonal to the surface of the light sensing area of the image sensor forms an inclined surface.

Abstract: Disclosed are techniques for compressing data of an image using multiple processing cores. The techniques include obtaining, using a first (second, etc.) processing core, a first (second, etc.) plurality of reconstructed blocks approximating source pixels of a first (second, etc.) portion of an image and filtering, using the first processing core, the first plurality of reconstructed blocks. The filtering includes enabling application of one or more filters to a first plurality of regions that include pixels of the first plurality of reconstructed blocks but not pixels of the second plurality of reconstructed blocks. The filtering further includes disabling application of the one or more filters to a second plurality of regions that include pixels of the first plurality of reconstructed blocks and pixels of the second plurality of reconstructed blocks.

Abstract: The present disclosure relates to a fabricating method of a semiconductor memory device including the following steps. Firstly, a substrate is provided, and a plurality of gate structures is formed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. Next, a plurality of isolation fins is formed on the substrate, wherein each of the isolation fins is parallel with each other and extends along the first direction, over each of the gate structures respectively. After forming the isolation fins, at least one bit line is formed on the substrate, extending along a second direction being perpendicular to the first direction, wherein the at least one bit line comprises a plurality of pins extending along a direction being perpendicular to the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

Abstract: Disclosed are techniques for compressing data of an image. Intermediate pixels may be determined. Each location of the image may be associated with a block of a plurality of blocks of a first size and a block of a plurality of blocks of a second size. For each block of the first size and of the second size, a first cost for a first mode and a second cost for a second mode may be determined in parallel using the intermediate pixels. A final mode and a final block size may be selected for each location of the image using the first cost and the second cost for each of a respective block of the first size and a respective block of the second size associated with a corresponding location. Final pixels may be determined, and a representation of the image may be obtained based on the final pixels.

Abstract: Disclosed are apparatuses, systems, and techniques for real-time codec encoding of video files using hardware-assisted accelerators that utilize a combination of parallel and sequential processing, in which at least a part of intra-frame block prediction is performed with parallel processing.

Abstract: A surface-mount device platform includes a surface-mounting region, a connection region, and a bendable region therebetween, each including a respective part of a base substrate. The base substrate includes electrically-conductive layers interspersed with electrically-insulating build-up layers. Each of the surface-mounting region, the connection region, and the bendable region spans between a bottom substrate-surface and a top substrate-surface of the base substrate. The surface-mounting region further includes an electrically-insulating first top rigid-layer, and device bond-pads exposed on a top surface of the first top rigid-layer facing away from the top substrate-surface in the surface-mounting region.

Abstract: The disclosure provides a semiconductor memory device and a method of forming a semiconductor device. The semiconductor memory device includes a substrate and a first pattern. The first pattern is disposed on the substrate and extends along a first direction. The first pattern includes an extension portion and two end portions. The two end portions include a first end pattern and a second end pattern, respectively. The extension portion has a first width. The first end pattern includes an outer widened portion and an inner widened portion. The maximum width of the outer widened portion and the maximum width of the inner widened portion are different from each other, and both are greater than the first width of the extension portion of the first pattern.

Abstract: Embodiments disclose a buried bit line structure, a method for fabricating the buried bit line structure, and a memory. The buried bit line structure includes: a substrate having a bit line trench; a bit line metal filled in the bit line trench; and a bit line contact filled in the bit line trench and positioned on the bit line metal, where an arc-shaped contact surface is provided between the bit line contact and the bit line metal. By setting a contact surface between the bit line contact and the bit line metal to be the arc-shaped contact surface, a contact area between the bit line contact and the bit line metal is increased, electrical conductivity of the bit line structure is enhanced.

Abstract: A receptacle connector for mating with a plug connector having a mating tongue and a latch thereof, includes an insulative housing defining a mating slot extending along a longitudinal direction to receive the mating tongue of the plug connector, and an outer metallic shield defining a primary space to receive the housing and a secondary space communicatively beside the primary space to receive the latch of the plug connector. A plurality of contacts are disposed in the housing to mechanically and electrically connect to the mating tongue. An inner metallic shield is attached upon a long side of the housing to separate the primary space and the secondary space from each other in a transverse direction perpendicular to the longitudinal direction.

Abstract: The present disclosure provides a method of manufacturing a buried bit line structure and a buried bit line structure. The method of manufacturing a buried bit line structure includes: providing an initial structure, the initial structure including active region structures; forming an initial bit line trench, the initial bit line trench exposing the active region structure; forming a conductive structure, the conductive structure being located at the bottom of the initial bit line trench; forming a bit line contact structure, the bit line contact structure covering the conductive structure, and a top surface of the bit line contact structure being lower than a top surface of the active region structure; and forming an insulation structure, the insulation structure covering the bit line contact structure.

Abstract: The present invention is applicable to the technical field of marine equipment and provides a hybrid-driven mooring chain cleaning and structural inspection underwater robot and a working method thereof. The hybrid-driven mooring chain cleaning and structural inspection underwater robot includes at least one frame structure; a buoyancy system disposed on the frame structure and used for adjusting the buoyancy of the robot; a driving system disposed on the frame structure; underwater observation and communication systems disposed on the frame structure and used for underwater observation; a cleaning system disposed on the frame structure and used for cleaning a mooring chain; an active clasping/unclasping system disposed on the frame structure; and a structural inspection system disposed on the frame structure.

Abstract: A method of encapsulating a solid sample in a droplet, the method including flowing a continuous phase through a first fluid channel at a first flow rate; flowing a dispersed phase through a second fluid channel at a second flow rate, the dispersed phase including a plurality of particles, cells or beads; trapping the plurality of particles, cells or beads in a mixing region that receives the dispersed phase and the continuous phase; and reducing the first flow rate to encapsulate the trapped particles, cells or beads in droplets of the dispersed phase generated when the dispersed phase and the continuous phase exit the mixing region through an orifice.

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.