Abstract: The present disclosure provides a method of manufacturing a buried bit line structure and a buried bit line structure. The method of manufacturing a buried bit line structure includes: providing an initial structure, the initial structure including active region structures; forming an initial bit line trench, the initial bit line trench exposing the active region structure; forming a conductive structure, the conductive structure being located at the bottom of the initial bit line trench; forming a bit line contact structure, the bit line contact structure covering the conductive structure, and a top surface of the bit line contact structure being lower than a top surface of the active region structure; and forming an insulation structure, the insulation structure covering the bit line contact structure.

Abstract: The present invention is applicable to the technical field of marine equipment and provides a hybrid-driven mooring chain cleaning and structural inspection underwater robot and a working method thereof. The hybrid-driven mooring chain cleaning and structural inspection underwater robot includes at least one frame structure; a buoyancy system disposed on the frame structure and used for adjusting the buoyancy of the robot; a driving system disposed on the frame structure; underwater observation and communication systems disposed on the frame structure and used for underwater observation; a cleaning system disposed on the frame structure and used for cleaning a mooring chain; an active clasping/unclasping system disposed on the frame structure; and a structural inspection system disposed on the frame structure.

Abstract: A method of encapsulating a solid sample in a droplet, the method including flowing a continuous phase through a first fluid channel at a first flow rate; flowing a dispersed phase through a second fluid channel at a second flow rate, the dispersed phase including a plurality of particles, cells or beads; trapping the plurality of particles, cells or beads in a mixing region that receives the dispersed phase and the continuous phase; and reducing the first flow rate to encapsulate the trapped particles, cells or beads in droplets of the dispersed phase generated when the dispersed phase and the continuous phase exit the mixing region through an orifice.

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

Abstract: A chip comprises a semiconductor substrate having a first side and a second side opposite to the first side, a plurality of conductive metal patterns formed on the first side of the semiconductor substrate, a plurality of solder balls formed on the first side of the semiconductor substrate, and at least one code pattern formed using laser marking on the first side of the semiconductor substrate in a space free from the plurality of conductive metal patterns and the plurality of solder balls, wherein the at least one code pattern is visible from a backside of the chip, the at least one code pattern represents a binary number having four bits; and the binary number represents a decimal number to represent a tracing number of the chip.

Abstract: In some embodiments, a method receives a time period in which video files will be delivered through a plurality of nodes. The method determines a plurality of user accounts that may use a video delivery system to deliver the video files in the time period; generates probabilities of which nodes may be used for each of the plurality of user accounts in the time period; and generates probabilities of which video files may be accessed by each of the plurality of user accounts. A list of video files is generated for a node based on the probabilities of which video files may be accessed and the probabilities of which nodes may be used for each of the plurality of user accounts. The method causes at least a portion of the list of video files for the node to be stored on the node.

Abstract: The invention discloses a semiconductor memory device, which is characterized by comprising a substrate defining a cell region and an adjacent periphery region, a plurality of bit lines are arranged on the substrate and arranged along a first direction, each bit line comprises a conductive part, and the bit line comprises four sidewalls, and a spacer surrounds the four sidewalls of the bit line, the spacer comprises two short spacers covering two ends of the conductive part, two long spacers covering the two long sides of the conductive part, and a plurality of storage node contact isolations located between any two adjacent bit lines, at least a part of the storage node contact isolations cover directly above the spacers. The structure of the invention can improve the electrical isolation effect, preferably avoid leakage current and improve the quality of components.

Abstract: A full-fiber burner brick and a preparation method thereof, comprising mixing alumina crystal fiber and amorphous ceramic fiber with both of them being a combination of fibers of different lengths gradations, and moreover adding fine powder fillers of different particle size gradations and supplementing other additives. This enables the internal structure of the product more uniform, increases the bulk density of the product, and also benefits the suction filterability of fiber cotton blank, and is conducive to forming and improving the strength of the blank. The surface of the brick body is further provided with a coating, which can effectively protect the cotton fiber of the brick body fiber from harsh environments, improve its high temperature resistance, and help to extend the service life of the burner brick.

Abstract: A semiconductor structure, a fabricating method thereof and a semiconductor device, the structure includes a substrate having a STI region and an AA, with an upper surface of the STI region lower than an upper surface of the AA; a stacked covered on the substrate; a first insulating layer covered the stacked structure, a second insulating layer covered the first insulating layer, and a third insulating layer covered the second insulating layer, over the STI region; a first insulating layer covered the stacked structure, over the AA, with an upper surface of the first insulating layer coplanar with an upper surface of the third insulating layer. The structure provides a semiconductor structure having a flat upper surface, avoiding polishing the first insulating layer over the AA to level with the first insulating layer over the STI region, greatly increasing the leakage risk, and reducing working stability of semiconductor devices.

Abstract: The present disclosure relates to a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate, an active structure, and a shallow trench isolation. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments, with the first active fragments and the second active fragments parallel and separately extended along a first direction. A plurality of first openings disposed in the substrate, between two adjacent ones of the first active fragments, and a plurality of second openings disposed in the substrate, between two adjacent ones of the second active fragments, wherein an aperture of the second openings is greater than an aperture of the first openings. The shallow trench isolation is disposed in the substrate to fill in the first openings and the second openings, and to surround the active structure.

Abstract: Disclosed herein are highly sensitive immunoassays that utilize a capture/release mechanism to reduce non-specific binding and achieve detection with attomolar-level sensitivity. Kits that can be used for carrying out these highly sensitive immunoassays are also disclosed herein.

Abstract: An active-pixel device assembly with stray-light reduction includes an active-pixel device including a semiconductor substrate and an array of active pixels, a light-transmissive substrate disposed on a light-receiving side of the active-pixel device, and a rough opaque coating disposed on a first surface of the light-transmissive substrate and forming an aperture aligned with the array of active pixels, wherein the rough opaque coating is rough so as to suppress reflection of light incident thereon from at least one side. A method for manufacturing a stray-light-reducing coating for an active-pixel device assembly includes depositing an opaque coating on a light-transmissive substrate such that the opaque coating forms a light-transmissive aperture, and roughening the opaque coating to form a rough opaque coating, said roughening including treating the opaque coating with an alkaline solution.

Abstract: A stereoscopic warehousing equipment comprising a conveying line assembly, a left storage assembly located at left end of the conveying line assembly, a right storage assembly located on tright end of the conveying line assembly, and a transferring carrying assembly arranged above the conveying line assembly and located between the left storage assembly and the right storage assembly, wherein the conveying line assembly comprising a conveying line mounting frame, an upper speed-chain conveying line and a lower speed-chain conveying line, wherein the conveying line mounting frame is provided with a lifting conveying platform located at front end of the upper and lower speed-chain conveying lines, wherein the lifting conveying platform comprising an electric lifting platform and a middle speed-chain conveying line, wherein the transferring carrying assembly comprising a transferring carrying portal frame, a horizontal driving linear module, a left carrying mechanism and a right carrying mechanism.

Abstract: An image sensor module comprises an image sensor having a light sensing area, a cover glass for covering the light sensing area, a dam between the image sensor and the cover glass, which surrounds the light sensing area, and has an outer wall and an inner wall, where a cross-section of the inner wall parallel to the surface of the light sensing area of the image sensor forms a sawtooth pattern and/or, where a cross-section of the inner wall orthogonal to the surface of the light sensing area of the image sensor forms an inclined surface.

Abstract: A forming method of a semiconductor structure includes the following: providing a semiconductor substrate formed with a first mask layer having a preset pattern; forming a second mask layer having a first mask pattern on a surface of the first mask layer, wherein the first mask pattern includes a plurality of first sub-patterns arranged in sequence; forming a second mask pattern in the second mask layer through the first mask pattern in a self-alignment manner, wherein the second mask pattern includes the first sub-patterns of the first mask pattern and second sub-patterns corresponding to the first sub-patterns; etching the first mask layer based on the first sub-patterns and the second sub-patterns of the second mask pattern to convert the preset pattern into an active area pattern; and defining active areas in the semiconductor substrate based on the active area pattern.

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

Abstract: Technologies directed to device detection and locationing are described. One method includes establishing a first wireless connection between a first wireless device and a second wireless device on a first channel. The first wireless device sends to the second wireless device a first indication that the first wireless device is to operate in an off-channel mode with a third wireless device at a first location a Fine Timing Measurement (FTM) procedure. The first wireless device performs a first FTM process between the first wireless device and the third wireless device. The first device determines first timing data including a signal round trip time (RRT) associated with the first FTM process and determines a first distance between the first wireless device and the third wireless device based on the first timing data. A second location of the first wireless device is determined using the first distance.

Abstract: A geometric model-based evaluation method, system, and apparatus for a key performance indicator in a production procedure are disclosed. The method includes extracting a geometric characteristic and a characteristic attribute thereof from a product model; converting the geometric characteristic into a process characteristic so as to obtain the steps of a process related to a whole production procedure of producing a product, and devices corresponding to the steps of the process; and based on the steps of the process related to the production procedure and the devices corresponding to the steps of the process, simulating the whole industrial manufacturing procedure of the product, and outputting the KPI of the industrial manufacturing. At least one embodiment can evaluate the KPI of the whole industrial manufacturing procedure of the product according to the product model.

Abstract: The present disclosure relates to a fabricating method of a semiconductor memory device including the following steps. Firstly, a substrate is provided, and a plurality of gate structures is formed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. Next, a plurality of isolation fins is formed on the substrate, wherein each of the isolation fins is parallel with each other and extends along the first direction, over each of the gate structures respectively. After forming the isolation fins, at least one bit line is formed on the substrate, extending along a second direction being perpendicular to the first direction, wherein the at least one bit line comprises a plurality of pins extending along a direction being perpendicular to the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

Abstract: The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.