Abstract: An information processing method and an electronic device are provided. The method includes receiving first information inputted by a user in a first input box, and displaying a second input box in a case that the first information does not match the first input box, where the second input box includes a part or all of the first information.

Abstract: A method of compressing and storing preview video includes performing colorspace-reduction image compression on a reference frame of a video to generate a colorspace-reduced reference frame; determining difference blocks representing areas of a subsequent image frame that differ from the reference frame and generating a difference frame comprising colorspace-reduced image data of the difference blocks; generating a video stream comprising a color palette, the colorspace-reduced reference frame, and the difference frame, and storing the video stream in an extreme low-voltage memory; and injecting, into the video stream prior to storing the video stream in the extreme low-voltage memory, a plurality of resynchronization codes for each reference frame and a plurality of resynchronization codes for each difference frame, the resynchronization codes comprising a byte sequence unique to resynchronization codes.

Abstract: The present invention provides a manufacturing method of a semiconductor device and a semiconductor device. A semiconductor device is provided, the semiconductor device includes a substrate, a stacked structure disposed on the substrate, the substrate comprises a cell array region, a peripheral circuit region and a middle region between the cell array region and the peripheral circuit region, the stacked structure comprises a first support layer, a first trench located in the middle region, a second support layer located on an upper surface of the stacked structure, wherein parts of the second support layer is disposed in the first trench, a portion of a sidewall of the first support layer directly contacts a portion of a sidewall of the second support layer, and a capacitor structure located in the cell array region.

Abstract: A plurality of tracking cameras is pointed towards a routine hovering area of an in-the-field sports participant who routinely hovers about that area. Spots within the hovering area are registered relative to a predetermined multi-dimensional coordinates reference frame (e.g., Xw, Yw, Zw, Tw) such that two-dimensional coordinates of 2D images captured by the tracking cameras can be converted to multi-dimensional coordinates of the reference frame. A body part recognizing unit recognizes 2D locations of a specific body part in the 2D captured images and a mapping unit maps them into the multi-dimensional coordinates of the reference frame. A multi-dimensional curve generator then generates a multi-dimensional motion curve describing motion of the body part based on the mapped coordinates (e.g., Xw, Yw, Zw, Tw). The generated multi-dimensional motion curve is used to discover cross correlations between play action motions of the in-the-field sports participant and real-world sports results.

Abstract: A receptacle connector for mating with a plug connector having a mating tongue and a latch thereof, includes an insulative housing defining a mating slot extending along a longitudinal direction to receive the mating tongue of the plug connector, and an outer metallic shield defining an upper space to receive the latch of the plug connector, and a lower space communicatively below the upper space to receive the housing. A plurality of contacts are disposed in the housing to mechanically and electrically connect to the mating tongue. An inner metallic shield is attached upon the upper wall of the housing to separate the upper space and the lower space from each other in a vertical direction.

Abstract: The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.

Abstract: A receptacle connector for mating with a plug connector having a mating tongue and a latch thereof, includes an insulative housing defining a mating slot extending along a longitudinal direction to receive the mating tongue of the plug connector, and an outer metallic shield defining a primary space to receive the housing and a secondary space communicatively beside the primary space to receive the latch of the plug connector. A plurality of contacts are disposed in the housing to mechanically and electrically connect to the mating tongue. An inner metallic shield is attached upon a long side of the housing to separate the primary space and the secondary space from each other in a transverse direction perpendicular to the longitudinal direction.

Abstract: A method for heat-treating a silicon single crystal wafer to control a BMD density thereof to achieve a predetermined BMD density by performing an RTA heat treatment on a silicon single crystal wafer composed of an Nv region in a nitriding atmosphere, and then performing a second heat treatment, the method including: formulating a relational equation for a relation between BMD density and RTA temperature in advance; and determining an RTA temperature for achieving the predetermined BMD density according to the relational equation. Consequently, a method for heat-treating a silicon single crystal wafer for manufacturing an annealed wafer or an epitaxial wafer each having defect-free surface and a predetermined BMD density in a bulk portion thereof.

Abstract: The present invention discloses a LAN system, method and unit supporting dynamic self-adaptive network configuration. Through the integration of self-adaptive dynamic routing protocol with various nodes of network, the source node broadcasts and sends a message containing destination node information, and the intermediate node searches the destination node information in its connection state sheet and returns to the source node or adds its node information into the message and sends to other intermediate nodes based on the searching results, the intermediate node will modify its routing list and open the routing transfer function. The source node and the destination node will configure their routing lists respectively with the gateway and corresponding network interfaces through which the network segment of other node is reached to establish a routing connection. The system can automatically configure the network, and greatly decrease its dependence on the central node, increasing stability and reliability.

Abstract: According to some aspects of the present disclosure, a method for loading a visual localization map is provided. The method may include: localizing a current pose; predicting, based on the current pose, a set of group numbers to be loaded for the visual localization map, wherein each group number in the set of group numbers to be loaded corresponds to a sub-map file of the visual localization map, wherein the visual localization map includes a master map file and a plurality of sub-map files, wherein the plurality of sub-map files respectively store map data of corresponding groups obtained by grouping the visual localization map based on key frames, and wherein key frame index information for indexing the plurality of sub-map files is stored in the master map file; and loading corresponding sub-map files based on the group numbers in the set of group numbers to be loaded.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate having a cavity recessed from a top surface of the substrate toward a bottom surface of the substrate opposite to the top surface, wherein the cavity has a sidewall and a bottom surface, and the bottom surface of the cavity is substantially parallel to the top surface of the substrate; a light source structure in the cavity, and the light source structure emitting a light from a sidewall of the light source structure; and a diffractive optical element (DOE) over the top surface of the substrate; wherein the sidewall of the cavity is a sloped surface, so that when the light is incident on the sidewall, the sloped surface reflects the incident light to generate a reflected light toward the DOE. Associated semiconductor structure and manufacturing method are also disclosed.

Abstract: This application provides a VR multi-screen display method and an electronic device. The method includes: An electronic device receives a first operation performed by a user in an application that supports VR; and the electronic device starts a VR multi-screen display mode in response to the first operation. Then, the electronic device receives a second operation performed by the user on a first application icon, and receives a third operation performed by the user on a second application icon; separately creates a first virtual screen corresponding to a first application and a second virtual screen corresponding to a second application in response to the second operation and the third operation; and displays content of the first application on the first virtual screen, and displays content of the second application on the second virtual screen.

Abstract: In a data read/write method, a storage server receives a write request of a client and performs storage. Each write request carries a to-be-written slice, an ID of a first storage device, and a virtual storage address of a first virtual storage block. If storage is performed continuously successfully from a start address within virtual storage space of a virtual storage block in the storage device, a successful continuous storage address range is recorded. For each storage device, all data within the successful continuous storage address range is successfully stored data. When receiving a read request of a client for an address segment within the address range, the storage server may directly return data that needs to be read to the client.

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.

Abstract: A system in package structure and an electrostatic discharge protection structure thereof are provided. The electrostatic discharge protection structure includes a redistribution layer and a first transistor array. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin end of at least one integrated circuit, the first electrode and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors of the transistors are coupled in parallel, and a plurality of second transistors of the transistors are coupled in parallel. The first transistors and the second transistors are configured to be turned on for dissipating an electrostatic discharge current.

Abstract: The present invention provides a manufacturing method of a semiconductor device and a semiconductor device. A semiconductor device is provided, the semiconductor device includes a substrate, a stacked structure disposed on the substrate, the substrate comprises a cell array region, a peripheral circuit region and a middle region between the cell array region and the peripheral circuit region, a first trench located in the middle region, a second support layer located on an upper surface of the stacked structure, wherein parts of the second support layer is disposed in the first trench, and a capacitor structure located in the cell array region.

Abstract: A method for manufacturing a silicon single crystal wafer for a multilayer structure device including: using a silicon single crystal wafer with oxygen concentration of 12 ppma (JEITA) or higher and composing an Nv region; and performing an RTA treatment in a nitrogen-containing atmosphere and a temperature of 1225° C. or higher, a mirror-polish processing treatment, and a BMD-forming heat treatment manufacturing a silicon single crystal wafer having at least a DZ layer with a thickness of 5 to 12.5 ?m and a BMD layer positioned immediately below the DZ layer and a BMD density of 1×1011/cm3 or higher from the silicon single crystal wafer surface. During device formation, the silicon wafer surface stress is absorbed immediately below a surface layer, distortion defects are absorbed by the BMD layer, device formation region strength is enhanced, and surface layer dislocation occurrence and extension is suppressed.

Abstract: An RFID tag reading system arranged to by carried by an operator while the operator's hands and arms remain free to accomplish tasks, the system including an RFID reader and a computer interconnected to the reader to control functions the reader and receive data generated by the reader, the computer being responsive to word commands from the operator to effectuate different functions of the reader.

Abstract: Provided are a capacitor and a filter and a redistribution layer structure including the same. The capacitor includes a first electrode, a second electrode, a third electrode, a dielectric layer, and a conductive through via. The second electrode is disposed above the first electrode. The third electrode is disposed between the first electrode and the second electrode. The dielectric layer is disposed between the first electrode and the third electrode and between the second electrode and the third electrode. The conductive through via penetrates the dielectric layer and the third electrode to be connected to the first electrode and the second electrode, and is electrically separated from the third electrode. The first electrode and the second electrode are signal electrodes, and the third electrode is a ground electrode.

Abstract: A plurality of high speed tracking cameras is pointed towards a routine hovering area of an in-the-field sports participant who routinely hovers about that area. Spots within the hovering area are registered relative to a predetermined multi-dimensional coordinates reference frame (e.g., Xw, Yw, Zw, Tw) such that two-dimensional coordinates of 2D images captured by the high speed tracking cameras can be converted to multi-dimensional coordinates of the reference frame. A body part recognizing unit recognizes 2D locations of a specific body part in the 2D captured images and a mapping unit maps them into the multi-dimensional coordinates of the reference frame. A multi-dimensional curve generator then generates a multi-dimensional motion curve describing motion of the body part based on the mapped coordinates (e.g., Xw, Yw, Zw, Tw).