Patents by Inventor Wei Hao

Wei Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220271217
    Abstract: A device includes a semiconductor substrate, a bottom conductive line, a bottom electrode, a magnetic tunneling junction (MTJ), and a residue. The bottom conductive line is over the semiconductor substrate. The bottom electrode is over the bottom conductive line. The MTJ is over the bottom electrode. The residue of the MTJ is on the sidewall of the bottom electrode and is spaced apart from the bottom conductive line.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 25, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen TIEN, Wei-Hao LIAO, Pin-Ren DAI, Chih-Wei LU, Chung-Ju LEE
  • Publication number: 20220256722
    Abstract: An electronic device package includes a substrate, at least one first electronic component and at least one electrical element. The substrate includes a first surface. The first surface comprises a plurality of electrical terminals including a first region and a second region, and a pitch of the electrical terminals of the first region is smaller than a pitch of the electrical terminals of the second region. The at least one first electronic component is electrically connected to the substrate and at least over the first region. The at least one electrical element is disposed above the first electronic component and farther from the substrate than the first electronic component. A number of the at least one electrical element under the first region is less than a number of the at least one electrical element under the second region.
    Type: Application
    Filed: February 5, 2021
    Publication date: August 11, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Hao CHANG
  • Publication number: 20220252828
    Abstract: An optical module includes a frame body and an optical element. The frame body includes at least one fixing portion, at least one frame portion, at least one shaft portion, and at least one reinforcement structure. The frame portion is connected to the fixing portion through the shaft portion. The reinforcement structure is connected to the frame portion and forms at least one fracture. The position of the fracture corresponds to the at least one shaft portion. The optical element is disposed in the frame portion. In addition, a projection device having the optical module is also provided.
    Type: Application
    Filed: January 6, 2022
    Publication date: August 11, 2022
    Applicant: Coretronic Corporation
    Inventor: Wei-Hao Chen
  • Patent number: 11405710
    Abstract: An earphone case includes a body, a storage member, a cover, and a reset member. The body has a chamber and a fixing base. The base is securely disposed in the chamber. The storage member is disposed in the chamber, located above the fixing base, contacted with the body, and has multiple first magnetic parts. The cover is pivotally connected to the storage member and the fixing base, and the cover has multiple second magnetic parts. The reset member is disposed above the fixing base and connected to the body and the storage member respectively. In close mode, the cover completely covers the storage member. The multiple first magnetic parts and second magnetic parts are magnetically attracted to each other. In open mode, the cover is relatively separated from the storage member and rotated at an angle, such that the cover partially overlaps with the storage member.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: August 2, 2022
    Assignee: Merry Electronics(Shenzhen) Co., Ltd.
    Inventors: Jia-Xin Lin, Wei-Hao Tu, Feng-Ping Chang
  • Publication number: 20220238683
    Abstract: A semiconductor device includes a first device formed over a substrate. The first device includes a first device formed over a substrate, and the first device includes a first gate stack structure encircling a plurality of first nanostructures. The semiconductor device includes a first epitaxy structure wrapping an end of one of the first nanostructures, and a second device formed over the first device, wherein the second device includes a second gate stack structure encircling a plurality of second nanostructures. The semiconductor device includes a second epitaxy structure wrapping an end of one of the second nanostructures, and the second epitaxy structure is directly above the first epitaxy structure.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hao WU, Zhi-Chang LIN, Ting-Hung HSU, Kuan-Lun CHENG
  • Publication number: 20220230963
    Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.
    Type: Application
    Filed: April 6, 2022
    Publication date: July 21, 2022
    Inventors: Wei-Hao Liao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai
  • Publication number: 20220231019
    Abstract: A semiconductor device includes: a first fin and a second fin extending from a substrate and an epitaxial source/drain region. The epitaxial source/drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and the first portion and the second portion are joined at a merging boundary. The epitaxial source/drain region further includes a first subregion extending from a location level with a highest point of the epitaxial source/drain region to a location level with a highest point of the merging boundary, a second subregion extending from the location level with the highest point of the merging boundary to a location level with a lowest point of the merging boundary, and a third subregion extending from the location level with the lowest point of the merging boundary to a location level with a top surface of an STI region.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Inventors: Wei Hao Lu, Yi-Fang Pai, Cheng-Wen Cheng, Li-Li Su, Chien-I Kuo
  • Publication number: 20220225543
    Abstract: A case is provided, including a shell, a fan frame, and a fan module. The shell is internally provided with a backplane and a motherboard, where the motherboard is connected to the backplane along a first axis, the backplane is connected with a plug connector, the plug connector includes a plug connector body and a plurality of connection terminals, and the connection terminals are located in the plug connector body. The fan frame bears the fan module, and the fan module includes a fan assembly and a matching connector. The matching connector is connected to the fan assembly, and the matching connector is connected to the plug connector along a second axis. The matching connector includes a matching connector body and a plurality of matching terminals, and the matching terminals are located in the matching connector body. The fan frame is fixed in the shell.
    Type: Application
    Filed: April 8, 2021
    Publication date: July 14, 2022
    Inventors: Jen-Hsien Lo, Wei-Hao Chen, Sheng-Chieh Tsai
  • Patent number: 11380271
    Abstract: Disclosed are a backlight driving method, a display driving method, a drive device and a display device. The backlight driving method includes: receiving a frame of backlight data, wherein the frame of backlight data includes a plurality of first control signals which are respectively applied to the plurality of switching channels and serve as the switching control signals, and a plurality of second control signal groups respectively corresponding to the plurality of first control signals, each of the plurality of second control signal groups includes a plurality of second control signals which are respectively applied to the plurality of output channels and serve as the output control signals, and the plurality of first control signals are modulated non-constant width pulse signals respectively; and driving the backlight unit to emit light by using the plurality of first control signals and the plurality of second control signal groups.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 5, 2022
    Assignees: BOE MLED TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qibing Gu, Wei Hao, Rui Liu, Lingyun Shi, Wei Sun, Ming Chen, Hong Yang
  • Patent number: 11372236
    Abstract: An optical module includes a frame body and an optical element. The frame body includes at least one fixing portion, at least one frame portion and at least one shaft portion connected to the fixing portion and the frame portion. The frame portion includes at least one main body, a plurality of positioning structures and at least one reinforcement structure. A part of an inner side surface of the main body is bended toward a thickness direction of the frame body to form the positioning structures, and the reinforcement structure is connected to the main body and extends in the thickness direction. The frame portion oscillates relative to the fixing portion around the shaft portion. In the thickness direction, a sum of a height of the reinforcement structure and a thickness of the main body is greater than a thickness of the shaft portion.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: June 28, 2022
    Assignee: Coretronic Corporation
    Inventor: Wei-Hao Chen
  • Publication number: 20220189770
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a fin-shaped structure on a substrate, forming a dielectric layer surrounding the fin-shaped structure, performing an anneal process to transform the dielectric layer into a shallow trench isolation (STI), removing the fin-shaped structure to form a trench, and forming a stack structure in the trench. Preferably, the stack structure includes a first semiconductor layer on the fin-shaped structure and a second semiconductor layer on the first semiconductor layer and the first semiconductor layer and the second semiconductor layer include different materials.
    Type: Application
    Filed: January 13, 2021
    Publication date: June 16, 2022
    Inventors: Shih-Wei Su, Hao-Che Feng, Hsuan-Tai Hsu, Chun-Yu Chen, Wei-Hao Huang, Bin-Siang Tsai, Ting-An Chien
  • Publication number: 20220189849
    Abstract: An electronic package includes an electronic component and a heat dissipation structure, wherein the heat dissipation structure has a plurality of bonding pillars, and a metal layer is formed on the bonding pillars, so as to stably dispose the heat dissipation structure on the electronic component via the bonding pillars and the metal layer.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 16, 2022
    Inventors: Jian-Dih Jeng, Chien-Yu Chen, Wei-Hao Chen
  • Patent number: 11362030
    Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive via is disposed within the first ILD layer. A plurality of conductive wires overlie the first ILD layer. A second ILD layer is disposed laterally between the conductive wires, where the second ILD layer comprises a first material. A sidewall spacer structure is disposed between the second ILD layer and the plurality of conductive wires. The sidewall spacer structure continuously extends along opposing sidewalls of each conductive wire. A top surface of the sidewall spacer structure is vertically above a top surface of the plurality of conductive wires, and the sidewall spacer structure comprises a second material different from the first material.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao
  • Publication number: 20220181218
    Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Wei-Hao Wu, Kuo-Cheng Chiang
  • Patent number: 11355603
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao Wu, Chia-Hao Chang, Chih-Hao Wang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin, Chia-Hao Kuo, Ke-Jing Yu
  • Patent number: 11355701
    Abstract: An integrated circuit includes a substrate, a dielectric layer, an etch stop layer, a bottom electrode, a resistance switching element, and a top electrode. The dielectric layer is over the substrate. The etch stop layer is over the dielectric layer, in which the dielectric layer has a first portion directly under the etch stop layer. The bottom electrode penetrates through the etch stop layer and the dielectric layer, in which the dielectric layer has a second portion directly under the bottom electrode, and a top of the first portion of the dielectric layer is lower than a top of the second portion of the dielectric layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih-Wei Lu, Pin-Ren Dai, Chung-Ju Lee
  • Patent number: 11357083
    Abstract: A light-emitting substrate and a method of driving the same, a light-emitting module, and a display apparatus are provided. The light-emitting substrate has a plurality of light-emitting areas. The light-emitting substrate includes: a base, a plurality of light-emitting components, a plurality of first power supply voltage signal lines, and a plurality of first control circuits. The plurality of light-emitting components are disposed on the base. The plurality of first power supply voltage signal lines are disposed on the base and arranged at intervals. The plurality of first control circuits are disposed on the base. One light-emitting component is located in one light-emitting area. Each of the first control circuits is coupled to a first electrode of one light-emitting component, and each of first power supply voltage signal lines is coupled to at least two first control circuits.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 7, 2022
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Hao, Feifei Wang, Wengang Su, Rui Shi, Lingyun Shi, Haiwei Sun, Ming Chen, Xue Dong
  • Publication number: 20220171169
    Abstract: A projection optical system, comprising: an image source; a lens group; a reflector; an image and an aperture, the lens group and the reflector form multiple optical paths between the image and image source, each optical path has a chief ray and a marginal ray, the chief ray of one of the optical paths forms a chief ray of a paraxial image height at the part where image source be near to the optical axis, the chief ray of another one of the optical paths forms a marginal ray of an off-axis image height at the part where image source be far from the optical axis; whereby forming a first point and a second point, the first point located at the origin and the second point is located in the first quadrant, and forming a third point and a fourth point, the third point located at the fourth quadrant and the fourth point is located in the second quadrant.
    Type: Application
    Filed: November 30, 2020
    Publication date: June 2, 2022
    Inventors: SHENG-CHE WU, YU-HUNG CHOU, WEI-HAO HUANG
  • Publication number: 20220174348
    Abstract: The present invention discloses a media playback apparatus having audio channel automatic selection mechanism that includes a communication circuit, a storage circuit and a processing circuit. The storage circuit stores computer executable commands The processing circuit executes the computer executable commands to execute a media playback method that includes the steps outlined below. An audio signal of a program corresponding to a channel is started to be received through the communication circuit. A detection module is operated to determine whether a supported audio channel mode of the audio signal is different from a previous supported audio channel mode. When the supported audio channel mode is different from the previous supported audio channel mode, a mode option is selected from at least one audio channel mode option supported by the audio channel mode according to a predetermined preference order. The audio signal is playback according to the selected mode option.
    Type: Application
    Filed: November 19, 2021
    Publication date: June 2, 2022
    Inventor: WEI-HAO CHEN
  • Patent number: 11333155
    Abstract: A thermal module including a first body, a second body, a first fan assembly, a second fan assembly, and a shaft is provided. The first body and the second body are slidably connected to each other and form an accommodating space together. The first fan assembly is disposed in the accommodating space and has a first hub and a plurality of first fan blades. The first hub is connected to the first body. The second fan assembly is disposed in the accommodating space and has a second hub and a plurality of second fan blades, and the second hub is connected to the second body. The first hub and the second hub overlap each other. The shaft is pivotally disposed in the first body and the second body and is engaged with the first fan assembly and the second fan assembly.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 17, 2022
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Jui-Min Huang, Chih-Wen Chiang, Chien-Chu Chen, Wei-Hao Lan, Ching-Ya Tu, Ken-Ping Lin