Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

Abstract: An electronic device including two bodies and at least one hinge structure including a connecting assembly and two rotating assemblies is provided. Each rotating assembly is rotatably connected to the connecting assembly and includes a bracket having at least one first sliding slot, a translation member translatably arranged on the bracket and having at least one second sliding slot, and a sliding member having at least one pillar penetrating the first second sliding slots at an overlapping position. The first and second sliding slots are inclined to each other and partially overlapped at the overlapping position. The two bodies are respectively connected to the sliding members. When each rotating assembly rotates, the connecting assembly guides the translation member to translate relative to the bracket to displace the overlapping position and drive the pillar to slide along the first and second slots to move the sliding member and the corresponding body.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A projection optical system with a concave reflector in the projection lens, comprising: an image source; a lens group; a reflector; an image and an aperture, the lens group and the reflector form multiple optical paths between the image and image source, each optical path has a chief ray and a marginal ray, the chief ray of one of the optical paths forms a chief ray of a paraxial image height at the part where image source be near to the optical axis, the chief ray of another one of the optical paths forms a marginal ray of an off-axis image height at the part where image source be far from the optical axis; wherein 2.2<F1/F2<3.0; 8<IMH/TR/Fno<19; 5<IMH*T1/T2<8. whereby the optimal optical performance of resolving power and optical path interference allowance will be achieved.

Abstract: An optical filter structure of an arbitrary combination of UV, R, G, B, and IR includes a substrate and a filter layer. The substrate is a wafer semiconductor sensor device and a product of light-transmitting device. The filter layer is formed on a surface of the substrate and is formed of a plurality of basic units arranged in an array. Each of the basic units includes a plurality of pixel filter films formed through vacuum coating, and the plurality of pixel filter films include an arbitrary combination of multiple ones of a UV pixel filter film, an R pixel filter film, a G pixel filter film, a B pixel filter film, and an IR pixel filter film, such that the plurality of pixel filter films allow light of corresponding wavelengths to pass therethrough.

Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

Abstract: A fixing mechanism is applied to an interface card assembly and an electronic apparatus. The fixing mechanism includes a movable window and an operation component. The movable window is slidably disposed on a casing of the interface card assembly. The operation component has a fixed end and a free end opposite to each other. The fixed end is disposed on the movable window. The free end is detachably engaged with the casing to position the movable window. The movable window is positioned on one of a first region and a second region of the casing for respectively fixing interface cards with different sizes to the casing.

Abstract: The disclosure provides an eye state assessment method and an electronic device. The method includes: obtaining an optic disc image area from a first fundus photography and generating multiple optic cup-to-disc ratio assessment results by multiple first models based on the optic disc image area; obtaining a first assessment result of an eye based on the optic cup-to-disc ratio assessment results; performing multiple data augmentation operations on the first fundus photography to generate multiple second fundus photographies; generating multiple retinal nerve fiber layer (RNFL) defect assessment results by multiple second models based on the second fundus photographies; obtaining a second assessment result of the eye based on the RNFL defect assessment results; and obtaining an optic nerve assessment result of the eye based on the first assessment result and the second assessment result.

Abstract: A method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. Forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.

Abstract: The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.

Abstract: A fan module including a body and a plurality of blades is provided. The body has a rotating axis and the body is telescopic along the rotating axis to have an elongated state and a shortened state. The blades are respectively disposed on the body and rotate along with the body along the rotating axis. At least a portion of each blade is flexible and a bending state of each blade is changed along with the elongated state or the shortened state of the body. An axial size of each blade along the rotating axis when the body is in the elongated state is greater than the axial size of each blade along the rotating axis when the body is in the shortened state.

Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a second conductive feature disposed over the first conductive feature. The second conductive feature includes a first sidewall, a first bottom, and a first angle between the first sidewall and the first bottom. The structure further includes a third conductive feature disposed over the dielectric layer and adjacent the second conductive feature. The third conductive feature includes a second sidewall, a second bottom, and a second angle between the second sidewall and the second bottom, the second angle is substantially different from the first angle, and the second and third conductive features are partially overlapping in an axis substantially parallel to a major surface of the substrate.

Abstract: In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.

Abstract: An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

Abstract: A method of controlling a driving circuit applicable to a light-emitting substrate which includes a light-emitting assembly including a plurality of light-emitting-element strings connected in parallel, each of the plurality of light-emitting strings comprising a plurality of light-emitting-elements connected in series, the driving circuit connected to the plurality of light-emitting-element strings via a wiring, wherein the method comprises: obtaining a wiring IR drop, a light-emitting element string IR drop, a voltage deviation, and a channel IR drop; obtaining a target power supply voltage according to the wiring IR drop, the light-emitting element string IR drop, the voltage deviation, and the channel IR drop; comparing the target power supply voltage with an output voltage to obtain a comparison result; generating an adjustment signal according to the comparison result; and adjusting the output voltage according to the adjustment signal.

Abstract: A server apparatus includes a casing having a first engaging structure, a tray mechanism including a tray, a handle and an elastic member, and a server module disposed on the tray. The handle is pivoted to the tray. The elastic member connected to the tray and has an interfering structure. The interfering structure interferes with the handle to position the handle for making the handle not interfere with the first engaging structure when the tray is inserted into the casing along an insertion direction.

Abstract: Methods for preparing a nanotube membrane for use in a pellicle membrane using dry printing are disclosed. Nanotube fibers are produced in a reaction vessel and dry sprayed onto a filter to form the nanotube membrane. The thickness of the nanotube membrane can be controlled by moving the reaction vessel and the filter relative to each other, or by further processing to reduce the thickness of the layer deposited onto the filter. This method reduces the number of process steps, reducing overall production time, and can also be used to produce larger membranes. The pellicle membrane can be formed with multiple layers and has a combination of high transmittance, low deflection, and small pore size. A conformal coating may applied to an outer surface of the pellicle membrane to protect the pellicle membrane from damage that can occur due to heat and hydrogen plasma created during EUV exposure.

Abstract: Methods and systems for IC photomask patterning are described. In some embodiments, a method includes inserting a dummy region in an IC design layout, the IC design layout includes an active region, and the active region and the dummy region is separated by a first distance. The method further includes performing one or more operations on the IC design layout, and the active region and the dummy region is separated by a second distance substantially less than the first distance. The method further includes performing a dummy region size reduction on the IC design layout to increase the second distance to a third distance substantially greater than the second distance, and the third distance is substantially greater than a minimum feature size to be patterned by a photolithography tool. The method further includes forming a photomask using the IC design layout.

Abstract: An infrared-cut filter structure is disclosed. The infrared-cut filter structure uses a glass substrate having an upper side and a lower side, with a first multilayer film formed on the upper side and a second multilayer film formed on the lower side so that the infrared-cut filter can effectively filter out infrared light and transmit visible light to produce normal colored images.