Abstract: A multi-axis prestressed double-tee beam and method for construction the same is provided, the prestressed double-tee beam includes a cantilever type and a simple-support type, the cantilever type is composed of a pair of laterally combined steel skeletons and each includes a flat elongate erect web having straight upper edge and a bowed lower edge, a pair of upward sloped upper flanges extended along the length of the web, an elongate groove of U-shaped section centrally extended between the upper flanges, a single lower flange extended along the length of the lower edge of the web, a bottom engageable with the lower end of the combined steel skeletons, a plurality of wedges inserted into the groove and a plurality of triangular reinforcement of different size spacedly secured to the lateral sides of the webs abutting the upper flanges, the simple-support type is mostly similar to the cantilever type except a slightly upward arcuate rectangular cross-section and equal sized triangular reinforcements, besides

Abstract: A system and method for translating source code, comprising high level source code with embedded SQL statements, to p-code or machine-language instructions by a one-pass parsing mechanism. The one-pass parsing mechanism generates executable code without the need to generate an intermediate file. Additionally, the p-code or machine-language instructions are annotated with references to the line numbers of the corresponding source code, thereby allowing a source level debugger to debug the source code with embedded SQL statements.

Abstract: Described herein is a system and method for enabling an application to pass a structure containing a pointer member to an external entity, wherein the application represents a computer program executing in a computer system, and the computer program is written in a computer programming language that does not support pointers. The application declares a variable V, a structure type having a member P, and a variable M of the structure type. The application invokes a function written in a computer programming language that supports pointers. A reference to the variable V is passed to the function. The function, when executed, obtains and returns an address of the variable V. The application sets the member P in the variable M equal to the address of the variable V. The application then passes the variable M to an external entity. In this manner, the present invention enables a structure having a pointer embedded therein to be passed to the external entity.

Abstract: A chip architecture standard merges dynamic random access memory (DRAM) macros and logic cores. The standard from merged DRAM and logic design provides the advantages of simplicity, high read and write access rates, lower power dissipation and noise suppression in system-on-chip designs. The architecture depends upon balanced clock distribution for its high performance and low clock skew to the DRAM macros and logic cores. Balanced wirings from output drivers of the control logic to corresponding inputs of the different DRAM macros minimize differences in address and control signal delays. Separated Vdd and Gnd power grids distribute power to the DRAM macros and the logic cores and incorporate decoupling capacitor arrays to provide noise suppression between the DRAM macros and logic and to minimize di/dt power supply fluctuations on chip performance.

Abstract: A two transistor one capacitor DRAM cell configured with respect to a bit line pair and a single word line in which the gates of the two transistors are connected to the single word line and one of the source/drains of each transistor is connected to a respective electrode of the capacitor and the other of the source/drains of the transistors is connected to a respective bit line of a complementary bit line pair. The storage capacitor is a three dimensional structure with both electrodes being electrically well isolated from electrodes of all other cell storage capacitors. A stacked in trench cell fabrication design is disclosed having a buried strap for connecting the outer electrode to a diffusion region of one transistor and a surface strap for connecting the inner electrode to a diffusion region of the second access transistor.

Abstract: Performance of a dual cascode voltage switch is improved and floating node effects including charge sharing and ratioing of output voltages are avoided by constituting the true and complement logic trees as pass gates of equal height, preferably limited, where possible, to a single transistor. The logic trees have substantially identical transistor layout configurations and different logic functions are established by selective connection of control and conduction terminals of the pass gates to reference logic level voltages of true and complement input variable signal values.

Abstract: A prestressed concrete tensioning system for a tensioning tendon in the construction of a prestressed concrete beam comprising an anchor seat and a prestressed tensioning device. The anchor seat embedded in one end of the beam and has spherical structure and inverse ratchet gripping device therein for adjustably holding one end of the tendon. The tensioning device has a hollow cylindrical housing including a hydraulic fluid chamber therein for slidably disposing a piston member in associated with a wedged surface grip means which are operated by hydraulic pressure for gripping and tensioning one end of the tendon, and a hemisphere concave in the forward end of the housing for engaging with the hemisphere convex of the anchor seat to obtain an universal joint effect. This disclosure is characterized in the prevention of shear and strength declination to the tendon and the risk to the ambient personnel.

Abstract: A multi-dirctional swivel joint for carrying loading members comprises a crosswise main body having a pair of first and a pair of second hollow cylinder members perpendicular to one another each having connected with a stepped neck member at their free end and pivotally and intersectionally coupled with a pair of lug members so as to permit the main body swiveling alternatively therewithin in multi-directions. A piston member slidingly disposed into each of the hollow cylinder members for defining a pair of first and second cylinder chambers which respectively communicate with an ambient hydraulic compressor via a pair of the first and second conduits through the piston member therein, in addition to a retaining ring sleeved on the free end of the piston member and secured by nut. So that the coupling of the main body with the lug members can be tightened or released upon the alternative exertion of the hydraulic force from the ambient compressor.

Abstract: A single sequential timing chain provides inadequate precision of reset-pulse timing and inadequate reset-pulsewidth control for high-performance memories or register files incorporating dynamic circuits. Also, in such circuits, an inevitable lengthening of pulses, from input to output, ensues. These shortcomings are eliminated by the disclosed multiple-branch circuits, which provide for the generation of appropriate control pulses, and by employment of evaluation-path pulsewidth-shortening circuits appropriately interconnected to the control-generation circuits.

Abstract: An improved tape winding linkage is disclosed. It comprises: (a) a deck, a gear shaft, a tape loading gear, and a guiding slot formed on the deck; (b) a first link having first and second joints, the first link being connected to the gear shaft at the first joint thereof; (c) a second link having first, second, and third joints, wherein the second link is divided into a first portion and a second portion intersecting at an angle at the second joint of the second link, and the second link further comprises a guiding pin located at the an under surface of the second joint to be received by and slide along the guiding slot of the deck; (d) a third link having first and second joints; (e) an inclined pole base connected to the third link at the second joint of the third link; and (f) an inclined pole base guiding pin provided at an under surface of the inclined pole base to be received by and slide along the guiding slot of the deck.

Abstract: A hydraulic grip suitable for use in both tensile and compressive loading of a specimen comprises generally a main body and an outer housing to form a pair of annular chamber thereinbetween. Hydraulic fluid under pressure alternately introduced into the chambers forces the outer housing to move up or downward relative to longitudinal axis of the main body. A cooling circulation may be established between the grip and a compressor so that the testing can be performed in high temperature. This grip also facilitates a rapid replacement of different grip jaws.

Abstract: A two transistor one capacitor DRAM cell configured with respect to a bit line pair and a single word line in which the gates of the two transistors are connected to the single word line and one of the source/drains of each transistor is connected to a respective electrode of the capacitor and the other of the source/drains of the transistors is connected to a respective bit line of a complementary bit line pair. The storage capacitor is a three dimensional structure with both electrodes being electrically well isolated from electrodes of all other cell storage capacitors. A stacked in trench cell fabrication design is disclosed having a buried strap for connecting the outer electrode to a diffusion region of one transistor and a surface strap for connecting the inner electrode to a diffusion region of the second access transistor.

Abstract: Sequentially terminated write enable pulses applied to respective input ports of a multi-port memory cell is effective to establish a priority among those input ports and provide unconditionally unambiguous writing to a memory cell when write operations are concurrently attempted at two or more ports of that cell, as may be encountered during rigorous testing procedures. Memory structure, particularly that of the input port circuits, is simplified and operational speed is enhanced since signal propagation through a comparator or logic circuit is avoided. Time required for testing of large memory arrays is also significantly reduced.

Abstract: A high-performance register file is implemented in a multi-block structure consisting of sub-arrays and associated multiplexing circuits. For a given port, the outputs of all multiplexer circuits are dotted together to form a single global output. The multiplexer circuits may be completely external to the cells ("standard" approach), or distributed and integrated into the cells ("alternate" approach). The register cells arranged as such, may or may not contain extra latches, pass gates, and controls arranged so that the file may be fully tested via LSSD.

Abstract: A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator.

Abstract: A high density substrate plate DRAM cell memory device and process are described in which a buried well region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by ion implantation and diffusion to intersect the walls of the deep trenches.

Abstract: A two transistor one capacitor DRAM cell configured with respect to a bit line pair and a single word line in which the gates of the two transistors are connected to the single word line and one of the source/drains of each transistor is connected to a respective electrode of the capacitor and the other of the source/drains of the transistors is connected to a respective bit line of a complementary bit line pair. The storage capacitor is a three dimensional structure with both electrodes being electrically well isolated from electrodes of all other cell storage capacitors. A stacked in trench cell fabrication design is disclosed having a buried strap for connecting the outer electrode to a diffusion region of one transistor and a surface strap for connecting the inner electrode to a diffusion region of the second access transistor.

Abstract: A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator.

Abstract: A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.

Abstract: Disclosed is a Dynamic Random Access Memory (DRAM) cell which includes a storage capacitor disposed in a trench formed in a semiconductor substrate and an access transistor disposed in a well which is opposite in conductivity type to that of the substrate and a buried oxide collar which surrounds an upper portion of the trench.