Abstract: A hardware design technique allows checking of design system language (DSL) specification of an element and schematics of large macros with embedded arrays and registers. The hardware organization reduces CPU time for logical verification by exponential order of magnitude without blowing up a verification process or logic simulation. The hardware organization consists of horizontal word level rather than bit level. A memory array cell comprises a pair of cross-coupled inverters forming a first latch for storing data. The first latch has an output connected to a read bit line. True and complement write word and bit line input to the first latch. A first set of pass gates connects between the true and complement write word and bit line inputs via gates and the input of said first latch. The first set of pass gates is responsive to a first clock via a second pass gate. A pair of cross-coupled inverters forms a second latch of a Level Sensitive Scan Design (LSSD).

Abstract: The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two kinds of 3D logic cells are disclosed. 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture. A high density “system on chip” architecture is described. The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer. A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described.

Abstract: A method of self-programmable Built In Self Test (BIST) for a memory (e.g., Dynamic Random Access Memory (DRAM)). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.

Abstract: A method for automatically tuning object sizes in an integrated circuit includes the steps of providing a circuit having objects disposed therein, inputting equations associated with the objects to provide a relationship between a size of the object and timing information of signals transmitted between the objects, extracting transition times of the signals transmitted between objects by simulating the circuit in operation by evaluating the equations and adjusting the sizes of the objects in the circuit according to the timing information and the transition times until user defined criteria are achieved for the circuit. Systems are also provided to carry out the method.

Abstract: A method of automatically selecting object size in an integrated circuit includes the steps of providing a circuit topology having objects disposed therein, inputting equations associated with the objects to provide sizing adjustment for the objects, assigning parameter values in the equations based on physical constraints of the circuit for one or more objects, selecting one or more objects to be sized, evaluating cones of influence for the objects selected to identify influenced objects influenced by a change in the selected object and computing for each selected object and influenced objects, a size in accordance with the associated equation until a user defined criteria is achieved for the circuit. A system for performing the method of the present invention is also described.

Abstract: Self-reset and write control circuits for high performance asynchronous multiport register files are disclosed. The high speed write operation is achieved by the combination of static data input and dynamic data control circuits. The write timing signal generation, true and complement address buffer, decoder and wordline drivers, and write enable circuits employ the advantages of a fully custom designed methodology with self-resetting complementary metal oxide semiconductor (SRCMOS) circuit techniques. Individual write enable pulses applied to respective input ports of a multiport register cell are effective to establish a priority among those input ports. In this design, the priority of the B-write-port over the A-write-port is established when both write ports address the same register. The present invention provides an effective input isolation/decoupling circuit technique which allows the input pulse widths to vary over a wide range.

Abstract: A memory (e.g. , Dynamic Random Access Memory (DRAM)) with self-programmable Built In Self Test (BIST). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.

Abstract: A differential cascode voltage switch circuit includes a plurality of devices wherein a portion of the plurality of devices have a low threshold voltage and a remainder of the plurality devices have a regular threshold voltage for providing a performance gain without a substantial increase in standby power wherein at least one device has regular threshold voltage between a supply voltage and a ground. A method of producing a multi-threshold voltage circuit includes the steps of defining between a supply voltage node and ground at least one regular threshold voltage device for producing a high resistance to reduce current leakage and defining low threshold voltage devices within the circuit for reducing leakage current.

Abstract: A body twist exercising toy, which includes a mounting base for fastening to the user's waist, a saucer turned about a pivot at a support arm at the mounting base, a buzzer and a digital display and a set of LEDs respectively mounted on the saucer on the outside, a battery mounted inside the saucer, switch means, and a circuit board mounted inside the saucer and connected to the battery through the switch means to control the operation of the buzzer, the digital display, and the LEDs, wherein when the user twist the body, the saucer is rotated, and a centrifugal force is produced to switch on switch means, causing the buzzer, the digital display and the LEDs to be driven by the circuit board to produce sound and lighting effects and to indicate the number of runs of the rotary motion of the saucer.

Abstract: A system and method for translating source code, comprising high level source code with embedded SQL statements, to p-code or machine-language instructions by a one-pass parsing mechanism. The one-pass parsing mechanism generates executable code without the need to generate an intermediate file. Additionally, the p-code or machine-language instructions are annotated with references to the line numbers of the corresponding source code, thereby allowing a source level debugger to debug the source code with embedded SQL statements.

Abstract: A twin-axis prestressed single-tee beam with lower flanges and process of construction is previded. The process includes construction of a cantilever prestressed beam and a simple-support prestressed beam. Both of them have a steel skeleton of roughly Y-shaped section including a pair of upward tilted flanges on the top and a pair of narrower flanges on the bottom. The steel skeleton of a cantilever prestressed beam has a flat top and a arcuate bottom, and the steel skeleton of a simple-support prestressed beam has an upwardly arcuate generally rectangular body. Pressures are applied to the upper and lower flange by a plurality of hydraulic presses, so as to force the skeletons to be deflected to become nearly straightened. Then mounts an outer mold conforming the outer shape of the skeletons prior to grouting the concrete. When the concrete is cured.

Abstract: A hardware design technique allows checking of design system language (DSL) specification of an element and schematics of large macros with embedded arrays and registers. The hardware organization reduces CPU time for logical verification by exponential order of magnitude without blowing up a verification process or logic simulation. The hardware organization consists of horizontal word level rather than bit level. Using the elimination process for elements which are difficult to be extracted in Boolean form the logic around and inside a memory structure can be verified. The resultant register array hardware organization can be verified to all pins and nets up to the storage element.

Abstract: A low-power pulse-to-static conversion latch circuit is disclosed. The circuit includes self-timed control and an n-bit latch array both designed utilizing self-resetting CMOS circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with self-resetting CMOS (SCRMOS) test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance.

Abstract: A multi-functional test machine is provided.

Abstract: Very fast very large scale integrated (VLSI) chips can be built-up from "self-resetting" or "self-timed" macros. An input isolator circuit provides an effective input isolation/decoupling which allows the input pulse widths to vary over a wide range. This avoids, for a large chip having many macros, a significant problem in insuring that the output from one macro is compliant with the input requirements of a receiving macro. Mixed static and dynamic circuits are used. The circuit comprises three stages. The input first stage is a static NOR circuit providing a pulse-chopping function. This first stage chops any too wide input pulse to the desired pulse width. The middle stage is a self-resetting complementary metal oxide semiconductor (SRCMOS) dynamic NOR circuit to capture input which is reset too soon. The last stage is a half-latch circuit to keep the dynamic node at constant output voltage level.

Abstract: A rotatably fastening blind rivet is provided. The blind rivet includes a tubular rivet body of ductile material and an elongate stem engaged into the rivet body which has a radially enlarged rivet head of hexagon configuration at one end having a serrated surface and a central bore, a threaded inner periphery of predetermined pitch and number of threads in an upper region and a progressively introversion inner periphery in a lower region of the body. The stem includes a cylinder shank of threaded outer periphery engageable with the threads of the rivet body, a breakneck on the top of the shank from which a tensioning rod of hexagon spiral outer periphery extends upward and is slidably engageable with the central bore of the rivet head and a terminal head of stiffness material at a lower end of the shank remote from the rod having serrated surface toward the shank.

Abstract: A quasi-synchronous DRAM circuit uses a plurality of asynchronous DRAM macros organized in memory banks. An interface conversion circuit receives external synchronous control signals and generates internal control signals for each of the plurality of asynchronous DRAM macros. A data buffer circuit is connected to each of the asynchronous DRAM macros by in internal input/output (I/O) bus. The interface conversion circuit controls the data buffer to provide synchronous burst of data through frequency conversion.

Abstract: A method of construction a prestressed cable-stay bridge is provided. The method includes the constructing at least a tower having a pier, a pair of masts and a girder between the masts for securing a deck, a main beam supported on the deck along a longitudinal direction of the bridge, a pair of sub-beams connect to two ends of the main beam and suspended from a plurality of temporal stay cables from the top of the masts, an upper portion and a plurality of segment secured on the top of the main beam and the sub-beam after the performance of on the spot prestressing procedure, a plurality of side reinforcements secured to the elongate gaps at two lateral side of the bridge, a plurality of permanent stay cables instead of the temporal stay cables for suspending the bridge from the inner side of the masts and a roadway paved on the top of the bridge.

Abstract: A layout compiler compiles from hardware description language (HDL) and schematic description of a design, which consists of dynamic random access memory (DRAM) components and logic components, to the layout of an integrated logic and DRAM system on a single integrated chip. The layout compiler creates the physical structure (floor-plan) of integrated logic/DRAM chips and generates on-chip interconnections between the DRAM components and logic components. By integrating logic and DRAM memory onto the same chip, the performance gap which is the difference between the logic processor's data processing rate and the DRAM memory's data access rate can be minimized. Further, the bandwidth between the logic processor and the DRAM memory can be increased significantly. The layout methods eliminate the off-chip drivers and heavy capacitive loads presented in the off-chip interconnections. Low power dissipation is a direct result of integrated logic/DRAM chip in high frequency operations.

Abstract: The computation speed of a fast X+2X adder is improved by restructuring the carry generate/propagate logic. The adder is implemented with a multi-bit generation/propagation circuit which takes full advantage of the fact that in the X+2X computation, the input X is left-shifted by one bit and then added to itself. Significantly simplified multi-bit carry generate and propagate functions, and therefore fast circuits, are the result.