Patents by Inventor Wei Hwang

Wei Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • STORED DON'T-CARE BASED HIERARCHICAL SEARCH-LINE SCHEME
    Publication number: 20080175030
    Abstract: In the proposed stored don't-care hierarchical search-line scheme, a content-addressable memory (CAM) is divided into several blocks. Each block contains a plurality of local search-lines, a global search-line, a buffer and a memory cell. Data are stored in the blocks in order according to the length of the prefix. Data with the longest prefix is stored at the bottommost, and its don't-care state is used as the control signal of the buffer to control whether to transfer the data on the global search-line to the local search-line or not. The local search-line then transfer the value into the memory cell. There is no complex control circuit and extra storage device needed. Moreover, because the control signal directly comes from the don't-care state, power consumption on search-lines can be effectively reduced with no increase of search delay.
    Type: Application
    Filed: February 15, 2007
    Publication date: July 24, 2008
    Inventors: Shu-Wei CHANG, Wei Hwang, Ming-Hung Chang, Po-Tsang Huang
  • BUTTERFLY MATCH-LINE STRUCTURE AND SEARCH METHOD IMPLEMENTED THEREBY
    Publication number: 20080177944
    Abstract: The present invention discloses a butterfly match-line structure and a search method implemented thereby, wherein the parallelism of the match lines is increased to shorten the search time, and a butterfly-type connection is used to reduce the power consumption and achieve the best energy efficiency. Via the butterfly-type connection, information can be reciprocally transmitted between the parallel match lines, which are independent originally. When a miss case occurs, more succeeding memory cells will not be compared but will be turned off. Thereby, the power consumption is reduced. Further, XOR-based conditional keepers are used to reduce the matching time and the power consumption. Besides, such a circuit is also used to shorten the delay time of the butterfly-type connection.
    Type: Application
    Filed: February 15, 2007
    Publication date: July 24, 2008
    Inventors: Po-Tsang Huang, Wei Hwang, Shu-Wei Chang
  • Pipeline-based reconfigurable mixed-radix FFT processor
    Publication number: 20080155003
    Abstract: The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to maintain the signal-to-noise ratio. Internal storage elements are required in the method to hold and switch intermediate data. With good circuit partition, the storage elements can adjust their capacity for different modes, from 16-point to 4096-point FFTs, by turning on or turning off the storage elements.
    Type: Application
    Filed: January 8, 2007
    Publication date: June 26, 2008
    Applicant: National Chiao Tung University
    Inventors: Chi-Chen Lai, Wei Hwang
  • XOR-based conditional keeper and an architecture implementing its application to match lines
    Patent number: 7358768
    Abstract: The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock signal synchronous with CAM (Content Addressable Memory) cells and cooperates with a floating signal from the floating node to create an XOR control signal, and the XOR control signal is transmitted to a P-type transistor to create a data signal to control the XOR-based conditional keeper so that the XOR-based conditional keeper can execute an appropriate corresponding action, which can replace the conventional keepers of merely “on” and “off” modes. Further, the XOR-based conditional keeper of the present invention can apply to the dynamic CAM match line architecture so that the dynamic match line can have lower power consumption, higher noise immunity, and high processing speed.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: April 15, 2008
    Assignee: National Chiao Tung University
    Inventors: Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang
  • Comparator eliminating need for one's complement logic for signed numbers
    Patent number: 7284028
    Abstract: An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: October 16, 2007
    Assignee: International Business Machines Corporation
    Inventors: Wei Hwang, Kun Wu
  • Method of etching uniform silicon layer
    Patent number: 7271102
    Abstract: A method of etching a silicon layer to avoid non-uniformity. First, a patterned silicon layer is provided. Next, an etching buffer layer is conformally formed on the surface and the top layer of the patterned silicon layer. Finally, the etching buffer layer and the patterned silicon layer are etched until the thickness of the patterned silicon layer is reduced. The conformal oxide layer provides etching resistance as an etching buffer layer, such that the etching rate is uniform on the whole subject matter, thereby, reducing the thickness of the patterned silicon layer uniformly after etching.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: September 18, 2007
    Assignee: AU Optronics Corporation
    Inventors: Chien-Chou Hou, Ching-Te Huang, Li-Wei Hwang, Shih-Kun Chen
  • Asynchronous first-in-first-out cell
    Patent number: 7260008
    Abstract: The present invention discloses an asynchronous first-in-first-out cell, wherein modified Muller C elements are used to reduce the complexity of the circuit of the asynchronous first-in-first-out cell; the asynchronous first-in-first-out cell of the present invention not only can be reusable, but also can apply to a single-supply-voltage system with a single clock frequency or multiple clock frequencies and a multiple-supply-voltage system with a single clock frequency or multiple clock frequencies. Further, when the asynchronous first-in-first-out cell of the present invention is applied to the interface circuit of a dual-supply-voltage 16-point radix-22 GALS-based FFT architecture, considerable power saving and latency reduction can be achieved.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: August 21, 2007
    Assignee: National Chiao Tung University
    Inventors: Yeh-Lin Chu, Wei Hwang
  • Clock switching circuit
    Patent number: 7259598
    Abstract: The present invention discloses a clock switching circuit, which comprises: a clock generator, receiving two different clock signals; a logic gate, coupled to an enable-signal generator and an output-clock generator, wherein during clock switching, the logic gate turns off output clock according to the signal edges of those two clock signals to avoid the problems of clock glitch and timing insufficiency, and the logic gate will not restore clock output until an appropriate timing occurs.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: August 21, 2007
    Assignee: National Chiao Tung University
    Inventors: Jian-Hua Wu, Wei Hwang
  • Clock switching circuit
    Publication number: 20070152719
    Abstract: The present invention discloses a clock switching circuit, which comprises: a clock generator, receiving two different clock signals; a logic gate, coupled to an enable-signal generator and an output-clock generator, wherein during clock switching, the logic gate turns off output clock according to the signal edges of those two clock signals to avoid the problems of clock glitch and timing insufficiency, and the logic gate will not restore clock output until an appropriate timing occurs.
    Type: Application
    Filed: April 19, 2006
    Publication date: July 5, 2007
    Inventors: Jian-Hua Wu, Wei Hwang
  • XOR-based conditional keeper and an architecture implementing its application to match lines
    Publication number: 20070103885
    Abstract: The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock signal synchronous with CAM (Content Addressable Memory) cells and cooperates with a floating signal from the floating node to create an XOR control signal, and the XOR control signal is transmitted to a P-type transistor to create a data signal to control the XOR-based conditional keeper so that the XOR-based conditional keeper can execute an appropriate corresponding action, which can replace the conventional keepers of merely “on” and “off” modes. Further, the XOR-based conditional keeper of the present invention can apply to the dynamic CAM match line architecture so that the dynamic match line can have lower power consumption, higher noise immunity, and high processing speed.
    Type: Application
    Filed: January 10, 2006
    Publication date: May 10, 2007
    Inventors: Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang
  • Asynchronous first-in first-out cell
    Publication number: 20070097771
    Abstract: The present invention discloses an asynchronous first-in-first-out cell, wherein modified Muller C elements are used to reduce the complexity of the circuit of the asynchronous first-in-first-out cell; the asynchronous first-in-first-out cell of the present invention not only can be reusable, but also can apply to a single-supply-voltage system with a single clock frequency or multiple clock frequencies and a multiple-supply-voltage system with a single clock frequency or multiple clock frequencies. Further, when the asynchronous first-in-first-out cell of the present invention is applied to the interface circuit of a dual-supply-voltage 16-point radix-22 GALS-based FFT architecture, considerable power saving and latency reduction can be achieved.
    Type: Application
    Filed: January 12, 2006
    Publication date: May 3, 2007
    Inventors: Yeh-Lin Chu, Wei Hwang
  • Power gating structure having data retention and intermediate modes
    Patent number: 7190187
    Abstract: The present invention provides a power gating structure having data retention and intermediate modes and able to operate under multiple modes. A conventional power gating structure has only turn-on and turn-off functions, and is used to suppress a leakage current problem which has become more and more serious in advance manufacture processes, under a turn-off mode. However, in a memory circuit, such as latch, register and SRAM, when the power gate is turned off, a new power gating structure is required for data retention. The power gating structure of the present invention can be set into one of 4 different operational modes: a data retention mode for maintaining the static noise margin of the memory, an intermediate mode for reducing the interference on ground and power levels, an active mode used when the circuit operates in normal condition, and a standby mode used when the circuit does not operate.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: March 13, 2007
    Assignee: National Chiao Tung University
    Inventors: Chung-Hsien Hua, Wei Hwang
  • Power gating structure having data retention and intermediate modes
    Publication number: 20060119393
    Abstract: The present invention provides a power gating structure having data retention and intermediate modes and able to operate under multiple modes. A conventional power gating structure has only turn-on and turn-off functions, and is used to suppress a leakage current problem which has become more and more serious in advance manufacture processes, under a turn-off mode. However, in a memory circuit, such as latch, register and SRAM, when the power gate is turned off, a new power gating structure is required for data retention. The power gating structure of the present invention can be set into one of 4 different operational modes: a data retention mode for maintaining the static noise margin of the memory, an intermediate mode for reducing the interference on ground and power levels, an active mode used when the circuit operates in normal condition, and a standby mode used when the circuit does not operate.
    Type: Application
    Filed: May 3, 2005
    Publication date: June 8, 2006
    Inventors: Chung-Hsien Hua, Wei Hwang
  • Configurable voltage generator
    Publication number: 20050174162
    Abstract: A configurable voltage generator is disclosed for generating multiple levels of output. It includes an oscillator module for generating a pumping signal, a digital to analog (D/A) converter coupled to the oscillator for generating one or more analog signals of a predetermined voltage level based on the pumping signal as configured by a set of inputs thereof, and a charge pump coupled to the D/A converter for producing a direct current (DC) output based on the analog signals generated by the D/A converter.
    Type: Application
    Filed: February 9, 2004
    Publication date: August 11, 2005
    Inventors: Tung-Shuan Cheng, Hung-Jen Liao, Wei Hwang
  • Dual-type thin-film field-effect transistors and applications
    Patent number: 6890766
    Abstract: A microelectronic device includes a gate layer adapted to receive an input voltage. An insulating layer is formed on the gate layer, and a conductive channel layer is formed on the insulating layer and carries current between a source and a drain. The conductive channel layer is adapted to provide a dual channel. The dual channel includes both a p-channel and an n-channel wherein one of the p-channel and the n-channel are selectively enabled responsive to the input voltage polarity. A method for forming the device and applications are also disclosed and claimed.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: May 10, 2005
    Assignee: International Business Machines Corporation
    Inventors: Thomas Doderer, Wei Hwang, Chang C. Tsuei
  • Method of etching uniform silicon layer
    Publication number: 20040106286
    Abstract: A method of etching a silicon layer to avoid non-uniformity. First, a patterned silicon layer is provided. Next, an etching buffer layer is conformally formed on the surface and the top layer of the patterned silicon layer. Finally, the etching buffer layer and the patterned silicon layer are etched until the thickness of the patterned silicon layer is reduced. The conformal oxide layer provides etching resistance as an etching buffer layer, such that the etching rate is uniform on the whole subject matter, thereby, reducing the thickness of the patterned silicon layer uniformly after etching.
    Type: Application
    Filed: June 20, 2003
    Publication date: June 3, 2004
    Applicant: AU Optronics Corp.
    Inventors: Chien-Chou Hou, Ching-Te Huang, Li-Wei Hwang, Shih-Kun Chen
  • Comparator eliminating need for one's complement logic for signed numbers
    Publication number: 20040088591
    Abstract: An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.
    Type: Application
    Filed: November 1, 2002
    Publication date: May 6, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Hwang, Kun Wu
  • Dual-type thin-film field-effect transistors and applications
    Publication number: 20030201495
    Abstract: A microelectronic device includes a gate layer adapted to receive an input voltage. An insulating layer is formed on the gate layer, and a conductive channel layer is formed on the insulating layer and carries current between a source and a drain. The conductive channel layer is adapted to provide a dual channel. The dual channel includes both a p-channel and an n-channel wherein one of the p-channel and the n-channel are selectively enabled responsive to the input voltage polarity. A method for forming the device and applications are also disclosed and claimed.
    Type: Application
    Filed: April 21, 2003
    Publication date: October 30, 2003
    Inventors: Thomas Doderer, Wei Hwang, Chang C. Tsuei
  • Merged logic and memory combining thin film and bulk Si transistors
    Patent number: 6620659
    Abstract: The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two kinds of 3D logic cells are disclosed. 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture. A high density “system on chip” architecture is described. The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer. A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: September 16, 2003
    Assignee: International Business Machines Corporation
    Inventors: Philip George Emmma, Wei Hwang, Stephen McConnell Gates
  • Memory array with salicide isolation
    Patent number: 6599793
    Abstract: The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate and second isolation devices aligned on the semiconductor substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are on the second isolation devices therefor have null memory function. A conductive structure is below a surface of the semiconductor substrate. The conductive structure is located between the first isolation devices. A conductive contact is on the conductive structure. The correspondence of the first isolation devices and the polysilicon lines can prevent the conductive structures from short effect.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: July 29, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Hung Chou, Jui-Lin Lu, Chong-Jen Huang, Shou-Wei Hwang, Hsin-Huei Chen