Patents by Inventor Wei Jen

Wei Jen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11463383
    Abstract: Presented herein are techniques for redacting mirrored network packets prior to providing the mirrored packets to an intended recipient application, such as a third-party analysis application. More specifically, a multi-destination packet redaction device obtains mirrored network traffic that comprises one or more mirrored network packets. The multi-destination packet redaction device filters the mirrored network traffic to determine an intended recipient application of the one or more mirrored network packets and applies a redaction process to redact one or more portions of at least one of the one or more mirrored network packets. The redaction process is customized based on one or more attributes of the intended recipient application.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: October 4, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Chih-Tsung Huang, Wei-Jen Huang, Kelvin Chan, Chiapeng Wu
  • Patent number: 11458164
    Abstract: The present invention provides a novel Streptococcus thermophilus strain ST4, and its use in manufacturing a medicament and/or food composition for treating and/or preventing an inflammatory disease and/or a cancer.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: October 4, 2022
    Assignee: SYNGEN BIOTECH CO., LTD.
    Inventors: Wei-Jen Chen, Shiuan-Huei Wu, Chiau-Ling Gung, Yu-Lun Tsai
  • Publication number: 20220302346
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a first semiconductor layer, an active region, a p-type or n-type layer, and a first metal element-containing structure. The first semiconductor layer has a surface including a first portion and a second portion. The active region is located on the first portion and includes AlGaInAs, InGaAsP, AlGaAsP or AlGaInP. The p-type or n-type layer includes an oxygen element (O) and a metal element, and is located on the second portion. The first metal element-containing structure is located on the p-type or n-type layer. The p-type or n-type layer physically contacts the first metal element-containing structure and the first semiconductor layer.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Inventors: Min-Hsun HSIEH, Yu-Tsu LEE, Wei-Jen HSUEH
  • Publication number: 20220302360
    Abstract: A semiconductor device is provided, which includes a semiconductor stack and a first contact structure. The semiconductor stack includes an active layer and has a first surface and a second surface. The first contact structure is located on the first surface and includes a first semiconductor layer, a first metal element-containing structure and a first p-type or n-type layer. The first metal element-containing structure includes a first metal element. The first p-type or n-type layer physically contacts the first semiconductor layer and the first metal element-containing structure. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm, and the first semiconductor layer includes a phosphide compound or an arsenide compound.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Inventors: Yu-Tsu LEE, Yi-Yang CHIU, Chun-Wei CHANG, Min-Hao YANG, Wei-Jen HSUEH, Yi-Ming CHEN, Shih-Chang LEE, Chung-Hao WANG
  • Publication number: 20220300065
    Abstract: The disclosure provides a handheld input device and an electronic system. The handheld input device includes a pen-shaped body, a flexible displacement sensor, and a processor. The flexible displacement sensor is disposed on the pen-shaped body, wherein the flexible displacement sensor deforms in response to a pressing force applied onto the flexible displacement sensor. The processor is coupled to the flexible pressure sensor and disposed in the pen-shaped body, wherein the processor is configured to perform: obtaining a specific displacement of the flexible displacement sensor; determining a stroke size of a representative object in a virtual environment based on the specific displacement of the flexible displacement sensor, wherein the representative object corresponds to the handheld device.
    Type: Application
    Filed: August 26, 2021
    Publication date: September 22, 2022
    Applicant: HTC Corporation
    Inventors: Wei-Jen Chang, Fu-Cheng Fan
  • Publication number: 20220285522
    Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.
    Type: Application
    Filed: May 26, 2022
    Publication date: September 8, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee, Tai-Ju Chen
  • Publication number: 20220285561
    Abstract: A method includes providing a semiconductor structure including a fin protruding from a substrate, where the fin includes first semiconductor layers and second semiconductor layers, recessing the fin to form a source/drain (S/D) recess, forming an S/D feature in the S/D recess, trimming the S/D feature, depositing a dielectric layer to cover the S/D feature, forming a contact hole in the dielectric layer to expose the S/D feature, and forming a metal contact in the contact hole.
    Type: Application
    Filed: September 1, 2021
    Publication date: September 8, 2022
    Inventors: Wei-Jen Lai, Wei-Yang Lee, De-Fang Chen, Ting-Wen Shih
  • Patent number: 11430380
    Abstract: The present disclosure relates to a pixel circuit including a light emitting element, a driving circuit, a first data storage circuit and a second data storage circuit. The driving circuit is electrically coupled to the light emitting element. The first data storage circuit is electrically coupled to the driving circuit, and is configured to transmit a first data signal to the driving circuit during a first frame period, so that the driving circuit drives the light emitting element according to the first data signal. The second data storage circuit is electrically coupled to the driving circuit, and is configured to receive a second data signal during the first frame period.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: August 30, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Po-Chun Lai, Wei-Ting Wu, Wei-Jen Chen, Chi-Fu Tsao, Yung-Chih Chen
  • Patent number: 11415806
    Abstract: A head mounted display apparatus includes a display, a focus adjuster and a controller. The display generates a display image. The focus adjuster is disposed between a target zone and the display, and is configured to adjust a position of a focus plan of the display image according to a control signal. The controller generates the control signal according to vision depth information.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: August 16, 2022
    Assignee: HTC Corporation
    Inventors: Cheng-Hsiu Tsai, Wei-Jen Chang, Fu-Cheng Fan
  • Publication number: 20220252883
    Abstract: A head mounted display apparatus includes a display, a focus adjuster and a controller. The display generates a display image. The focus adjuster is disposed between a target zone and the display, and is configured to adjust a position of a focus plan of the display image according to a control signal. The controller generates the control signal according to vision depth information.
    Type: Application
    Filed: February 5, 2021
    Publication date: August 11, 2022
    Applicant: HTC Corporation
    Inventors: Cheng-Hsiu Tsai, Wei-Jen Chang, Fu-Cheng Fan
  • Publication number: 20220254687
    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 11, 2022
    Inventors: Chung-Liang Cheng, Wei-Jen Chen, Yen-Yu Chen, Ming-Hsien Lin
  • Patent number: 11411107
    Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Jen Lai, Yen-Ming Chen, Tsung-Lin Lee
  • Patent number: 11404386
    Abstract: A semiconductor device package and manufacturing method thereof are provided. The semiconductor device package includes a first conductive structure, a second conductive structure, a connection element, a conductive member, an encapsulant and a binding layer. The first conductive structure includes a first circuit layer. The second conductive structure is disposed over the first conductive structure. The connection element is disposed on and electrically connected to the first circuit layer. The conductive member protrudes from the second conductive structure. The encapsulant is disposed between the first conductive structure and the second conductive structure. The binding layer is disposed between the second conductive structure and the encapsulant.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: August 2, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Po-Jen Cheng, Po-Hsiang Wang, Fu-Yuan Chen, Wei-Jen Wang
  • Publication number: 20220238337
    Abstract: A method includes placing a wafer into a production chamber, providing a heating source to heat the wafer, and projecting a laser beam on the wafer using a laser projector. The method further includes, when the wafer is heated by both of the heating source and the laser beam, performing a process selected from an epitaxy process to grow a semiconductor layer on the wafer, and an etching process to etch the semiconductor layer.
    Type: Application
    Filed: December 6, 2021
    Publication date: July 28, 2022
    Inventors: Yee-Chia Yeo, Syun-Ming Jang, Wei-Jen Lo
  • Publication number: 20220239331
    Abstract: Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Guo-Hau Gau, Ho-Chi Huang, Wei-Jen Chen, Chiou-Wei Tsai, Ju-Ya Chen, Mau-Lin Wu
  • Publication number: 20220229302
    Abstract: A head mounted display device includes a display, a light waveguide element, and a light shutter. The display periodically provides a display image. The light waveguide element receives the display image, generates a projection image according to the display image, projects the projection image from a second surface, and projects the projection image to a target zone from a first surface. The light shutter is adjacent to the second surface of the light waveguide element and is coupled to the light waveguide element. The light shutter is periodically disabled and enabled in an alternating manner.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Applicant: HTC Corporation
    Inventors: Cheng-Hsiu Tsai, Wei-Jen Chang, Fu-Cheng Fan
  • Patent number: 11380777
    Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: July 5, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee, Tai-Ju Chen
  • Publication number: 20220201382
    Abstract: Aspects of the present disclosure are directed to sensing earpiece positioning relative to user's left and right ears, and to routing audio signals based on the positioning. As may be implemented with various examples, for respective earpieces that generate audible sound, positions of opposing regions of one of the earpieces are detected relative to an ear, in which the opposing regions are along a perimeter of one of the earpieces. A sensor signal indicative of the detected positions is communicated, and audio signals of respective channels are routed to the earpieces, based on the sensor signal.
    Type: Application
    Filed: July 24, 2019
    Publication date: June 23, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Te-Yueh Lin, Wei Jen Chen, Chien Chung Chien
  • Patent number: 11368146
    Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 21, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Cheng-Yang Tsai, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Yu-Lin Chen
  • Patent number: 11360311
    Abstract: A head mounted display device includes a display, a light waveguide element, and a light shutter. The display periodically provides a display image. The light waveguide element receives the display image, generates a projection image according to the display image, projects the projection image from a second surface, and projects the projection image to a target zone from a first surface. The light shutter is adjacent to the second surface of the light waveguide element and is coupled to the light waveguide element. The light shutter is periodically disabled and enabled in an alternating manner.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: June 14, 2022
    Assignee: HTC Corporation
    Inventors: Cheng-Hsiu Tsai, Wei-Jen Chang, Fu-Cheng Fan