Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.

Abstract: A display device includes a display panel, a power integrated circuit, a comparison circuit and a selection circuit. The display panel is configured to receive a system cross voltage. The power integrated circuit is configured to provide the system cross voltage to the display panel and includes a current conversion circuit configured to convert a calibration current outputted by the display panel when displaying a calibration frame into a detection voltage. The comparison circuit is configured to compare the detection voltage with a threshold to generate a comparison result. The selection circuit is configured to determine a magnitude of the system cross voltage according to the comparison result. The power integrated circuit is configured to generate the system cross voltage according to the magnitude of the system cross voltage determined by the selection circuit to provide the system cross voltage to the display panel.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.

Abstract: At least some embodiments of the present disclosure relate to an electronic package structure. The electronic package structure includes an electronic structure, a wiring structure disposed over the electronic structure, a bonding element connecting the wiring structure and the electronic structure, and a reinforcement element attached to the wiring structure. An elevation difference between a highest point and a lowest point of a surface of the wiring structure facing the electronic structure is less than a height of the bonding element.

Abstract: An electronic package structure includes an electronic structure, a wiring structure, an electrical contact and a support layer. The wiring structure is located over the electronic structure. The electrical contact connects the wiring structure and the electronic structure. The support layer is disposed around the electrical contact and has a surface facing the electrical contact. The surface includes at least one inflection point in a cross-sectional view.

Abstract: The disclosure provides a handheld input device and an electronic system. The handheld input device includes a pen-shaped body, a flexible displacement sensor, and a processor. The flexible displacement sensor is disposed on the pen-shaped body, wherein the flexible displacement sensor deforms in response to a pressing force applied onto the flexible displacement sensor. The processor is coupled to the flexible pressure sensor and disposed in the pen-shaped body, wherein the processor is configured to perform: obtaining a specific displacement of the flexible displacement sensor; determining a stroke size of a representative object in a virtual environment based on the specific displacement of the flexible displacement sensor, wherein the representative object corresponds to the handheld device.

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: A single inductor multiple output regulator includes an inductor, a number of capacitors, a number of switches coupled with the capacitors and a control circuit coupled with the switches and configured to apply at least two multi-switching pulses to a multi-pulse controlled one of the switches in each cycle.

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are extended in width or length to connect to the power rail and the ground rail of the other one of the standard cells.

Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.

Abstract: An integrated circuit layout includes a first and a second standard cells abutting along a boundary line. The boundary line and a first active region of the first standard cell include a distance D1. A first gate line on the first active region protrudes from the first active region by a length L1. The boundary line and a second active region of the second standard cell include a distance D2. A second gate line on the second active region protrudes from the second active region by a length L2. Two first dummy gate lines and two second dummy gate lines are disposed at two sides of the first active region and the second active region and are away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

Abstract: A machine reading comprehension apparatus and method are provided. The apparatus receives a question and a text. The apparatus generates a plurality of first predicted answers and a plurality of first source sentences corresponding to each of the first predicted answers according to the question, the text, and the machine reading comprehension model. The apparatus determines a question category of the question. The apparatus extracts a plurality of special terms related to the question category and a plurality of second source sentences corresponding to each of the special terms from the text. The apparatus concatenates the question, the first source sentences, the second source sentences, the first predicted answers, and the special terms into an extended string. The apparatus generates a plurality of second predicted answers corresponding to the question according to the extended string and the micro finder model.

Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. A gate dielectric layer is disposed under the metal compound layer and contacts the substrate.

Abstract: A display device includes a display, an image beam shifter, and a light guiding component. The display generates an image beam. The image beam shifter receives the image beam and generates a projected image beam. The light guiding component receives the projected image beam to transport the projected image beam to different positions of a target zone in sequence. The image beam shifter projects the projected image beam to different positions of the light guiding component with time division.

Abstract: A machine reading comprehension method includes the following operations: performing a relation augment self attention (RASA) feature extraction process on at least one historical dialogue data and a current question data respectively to obtain at least one historical dialogue feature and a current question feature; and performing a machine reading comprehension (MRC) analysis according to the at least one historical dialogue feature and the current question feature to obtain a response output.

Abstract: A semiconductor device includes a dielectric layer, a first trench located in the dielectric layer, a first semiconductor located in the first trench, a second semiconductor layer and an electrical connector. The dielectric layer has a first surface. The second semiconductor layer includes an active portion connecting the first semiconductor layer, and the electrical connector is located on the first surface and connects the second semiconductor layer.

Abstract: An optoelectronic device includes a substrate, a first semiconductor stack located on the substrate, a second semiconductor stack located on the first semiconductor stack, and a first optical structure located between the first semiconductor stack and the second semiconductor stack. The first semiconductor stack includes a first semiconductor layer, a second semiconductor layer and a first active layer which emits or absorbs a first light with a first wavelength. The second semiconductor stack includes a third semiconductor layer, a fourth semiconductor layer and a second active layer which emits or absorbs a second light with a second wavelength smaller than the first wavelength. The first optical structure includes a plurality of first parts and a plurality of second parts. The first parts and the second parts are alternately arranged by a first period along a horizontal direction parallel to the substrate.

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first alignment pattern having a plurality of first scale patterns arranged in a first direction. The second semiconductor device is mounted over the first semiconductor device and includes a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.

Abstract: A semiconductor device is provided, which includes a substrate, a first semiconductor structure, a plurality of first holes, a first dielectric structure and a second semiconductor structure. The first semiconductor structure is located on the substrate. The first holes are periodically arranged in the first semiconductor structure. The first dielectric structure is filled in one or more of the first holes. The second semiconductor structure is located on the first semiconductor structure.