Abstract: Provided are catechol nanoparticles, catechol protein nanoparticles, and a preparation method and use thereof. The method includes: adding a tannin compound-containing natural herb medicine into water to obtain a mixture, and subjecting the mixture to heating reflux extraction to obtain a herb medicine extract and subjecting the herb medicine extract to fractionation to obtain the catechol nanoparticles.

Abstract: Embodiments of the disclosure provide a method, apparatus, device, and storage medium for content capturing. The method includes, in response to a capturing start instruction, presenting a capturing start page which including at least a capturing control; in response to detecting a trigger instruction for the capturing control, switching from the capturing start page to a capturing page for video capturing, the capturing page including at least a stop control and a pause control, and the stop control being presented in a more prominent way than the pause control; and in response to detecting a trigger instruction for the stop control, switching from the capturing page to a video editing page, the video editing page being used to edit a captured video. In this way, it is possible for users to quickly perform video capturing and directly enter the editing page to complete editing of a work.

Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout comprising a cell and a layout context in a vicinity of the cell; receiving from a library a set of context groups and a set of timing tables, wherein each of the context groups is associated with one of the set of timing tables; determining a representative context group for the cell through comparing the layout context of the cell with the set of context groups; and performing a timing analysis on the layout according to a representative timing table associated with the representative context group for the cell.

Abstract: Provided is a semiconductor device includes a gate electrode, a gate dielectric layer, a channel layer, an insulating layer, a first source/drain electrode and a second source/drain electrode, a second dielectric layer, and a stop segment. The gate electrode is located within a first dielectric layer that overlies a substrate. The gate dielectric layer is located over the gate electrode. The channel layer is located on the gate dielectric layer. The insulating layer is located over the channel layer. The first source/drain electrode and the second source/drain electrode are located in the insulating layer, and connected to the channel layer. The second dielectric layer is beside one of the first source/drain electrode and the second source/drain electrode. The stop segment is embedded in the second dielectric layer.

Abstract: Disclosed in the present disclosure is a double-deck multi-span bridge construction method. According to the double-deck bridge construction method of the present disclosure, construction is carried out by using a method of disassembling a support jig frame in a graded and span-separated mode, an upper chord jig frame and a lower chord jig frame can be used in a recycle manner, and construction costs are reduced. In addition, a construction period of building the support jig frame is shortened, and other construction operations can be synchronously carried out on a span in which the jig frame is disassembled, for example, fire retardant coating construction can be carried out on a mounted bridge deck after the jig frame is disassembled, and the construction period of a double-deck multi-span bridge is effectively shortened.

Abstract: A computer readable storage medium is provided. When contents of the computer readable storage medium are executed by a processor, multi-photon imaging may be performed on a histopathological section containing tumor environment information, and pathological partitioning of a tumor microenvironment may be further performed through image processing. A value of each collagen feature parameters, such as a morphological feature parameter, an energy feature parameter and a texture feature parameter, may be extracted from a tumor tissue region, an invasive margin (IM) region and a normal tissue (N) region. An inter-region difference and a variation may be calculated according to feature parameters of regions. A collagen feature scoring model may be established. A collagen feature score may be calculated with the collagen feature parameters input to the model.

Abstract: A method, computer program, or computer system is provided for compressing a neural network model. One or more blocks are identified from among a superblock corresponding to a multi-dimensional tensor associated with a neural network. A set of weight coefficients associated with the superblock is unified. A model of the neural network is compressed based on the unified set of weight coefficients.

Abstract: Systems, apparatus and methods are provided for managing a removable solid state storage system for data loss prevention. A method may include maintaining a standby mode for a timer of the removable solid state storage system until the removable solid state storage system is disconnected from an external power supply, setting an operation time interval on the timer, using the timer to count how long the removable solid state storage system has been disconnected, sending an interrupt to a storage controller of the removable solid state storage system from the timer when the timer counts to the operation time Interval, and performing data loss prevention operations using a power supplied by a removable battery.

Abstract: A secondary battery includes an electrode assembly including current collecting sections, an electrode terminal, and an adapter sheet connecting the current collecting sections to the electrode terminal. The electrode assembly includes active material layer(s), current collector(s) each including an insulating layer and first and second conductive layers sandwiching the insulating layer, and conductive structures each including first and second conductive members. A portion of the first conductive member extending beyond the second conductive member forms a current collecting section. The current collecting sections are laminated with each other, with one of the current collecting sections directly contacting the adapter sheet. Neighboring ones of the current collecting sections directly contact each other, without any second conductive member arranged therebetween.

Abstract: An electrode plate includes an active material layer, a current collector including an insulating layer and first and second conductive layers sandwiching the insulating layer, and a conductive structure. The conductive structure includes a first conductive member including a first section arranged along a side of the first conductive layer and a second section extending from the first section and beyond the current collector in a direction away from the active material layer, and a second conductive member including a first connecting section connected to the second conductive layer, a bent section connected to the first connecting section and bent towards the first conductive member relative to the first connecting section, and a second connecting section bent backward relative to the bent section to be sandwiched between the first section and the first conductive layer.

Abstract: A transmission processing method includes: obtaining, by an access network node, first information; and performing, by the access network node according to the first information, transmission processing on service data. The first information is used for indicating a type and/or a characteristic of the service data. The service data is a data packet and/or a data frame.

Abstract: Systems, apparatus and methods are provided for low temperature management of a storage system. An apparatus may include a temperature sensor to generate a temperature reading, a timer configured with a time interval, a backup battery, one or more non-volatile memory (NVM) devices and a storage controller. The storage controller may be configured to: maintain a standby mode for low temperature management until a host electronic system has been turned off, start the timer and check the temperature reading when the host electronic system is turned off, determine that the temperature reading is below a temperature threshold, set the time interval based on the temperature reading, receive an interrupt from the timer when the timer counts to the time Interval, and perform low-temperature management operations for data stored in the one or more NVM devices using power supplied by the backup battery.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: A near eye display system is provided. The near eye display system includes: a frame; a first near eye display mounted on the frame and configured to form a first image directly projected on a first retina of a first eye of a user; a second near eye display mounted on the frame and configured to form a second image directly projected on a second retina of a second eye of the user; and a processing unit located at the frame and configured to generate a display control signal to drive the first near eye display and the second near eye display.

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive an indication of an antenna port mapping from a network entity. The antenna port mapping may be between a tracking reference signal and a corresponding reference signal, the antenna port mapping indicating a mapping of a tracking reference signal port to a plurality of reference signal antenna ports associated with the corresponding reference signal. The UE may receive a tracking reference signal via the tracking reference signal port based on the antenna port mapping. The UE may perform a channel measurement procedure using the tracking reference signal based on the mapping.

Abstract: The invention discloses a synthesis method and device for rapidly producing lactide at high yield. The method comprises: adding a single component of lactic acid or two components of lactic acid and catalyst, passing the mixture through a mixer to enter an oligomer preparation system, increasing a residence time through bottom circulation, synthesizing oligomeric lactic acid, and passing a gas-phase component through a rectification system. With the adoption of the device, the lactide is capable of being efficiently synthesized, crude lactide with a yield of 94% to 98% is capable of being obtained.

Abstract: A display device and method of manufacturing thereof is provided. The display device includes: a substrate; a plurality of control transistors disposed in the substrate; a multi-layer interconnect (MLI) structure on the substrate; and a luminous device layer disposed on the MLI structure. The luminous device layer includes a plurality of sub-pixels corresponding to the plurality of control transistors, respectively. The MLI structure includes a plurality of routing features and at least one light blocking feature, and the plurality of routing features electrically connect each of the plurality of control transistors to the corresponding sub-pixel, and the at least one light blocking feature is operable to block stray light generated by the luminous device layer.

Abstract: A semiconductor structure includes: a logic device including a first power line and a second power line located on a same wiring layer, extending along a first direction and arranged in parallel along a second direction, the first direction and the second direction intersecting with each other and being parallel to a plane where the wiring layer is located; and a switch driving device, the switch driving device and the logic device being arranged in parallel along the first direction, the switch driving device including a first input line and a first output line located on the same wiring layer as the first power line, extending along the first direction and arranged in parallel along the second direction, the first output line being connected with the first power line or the second power line.

Abstract: A thin film transistor and a manufacturing method therefor, an array substrate, and a display panel and device. The thin film transistor includes: a gate (11) and an active layer (12) that are located on one side of a base substrate (10); a gate insulation layer (13) located between the gate (11) and the active layer (12); and a source (14) and a drain (15) that are spaced apart and both are in contact with the active layer (12), wherein a first ratio of the thickness of the gate insulation layer (13) and the thickness of the active layer (12) ranges from 3 to 4.

Abstract: A memory device includes a multi-layer stack, a channel layer, a memory material layer and at least three conductive pillars. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer and memory material layer penetrate through the plurality of conductive layers and the plurality of dielectric layers. The at least three conductive pillars are surrounded by the channel layer and the memory material layer, wherein the at least three conductive pillars are electrically connected to conductive layers respectively. The at least three conductive pillars includes a first, a second and a third conductive pillars disposed between the first conductive pillar and the second conductive pillar. A third width of the third conductive pillar is smaller than a first width of the first conductive pillar and a second width of the second conductive pillar.