Abstract: An Online Meta Learning (“OML”) framework is provided for learned image compression (“LIC”) based on a variable-rate Conditional Variational Auto-Encoder (“CVAE”) architecture. A computing system is configured to learn, from multiple training tasks of compression with different RD tradeoff ?s, a set of task-general meta parameters controlled by meta-control variables ?. Meta parameters learn a mapping between the meta-control variables ? and compression effects of different RD tradeoffs ?s. Meta-control variables ? are adaptively determined and transmitted on the fly to an encoder and a decoder of an image compression process, to accommodate the current compression need for any current test datum. A parallelized context computation method is also provided for an online CVAE-based meta-LIC architecture; since OML requires multiple iterations at an encoder, parallel context estimation substantially improves computational time in practice.

Abstract: A system may receive an input image block, and input the input image block into multiple models which may be trained using a plurality of different datasets of image blocks. Each model of the multiple models may be trained using a dataset having similar attributes. The system may determine a model having a highest compression efficiency from among the multiple models, and encode the input image block using the determined model.

Abstract: A transmission processing method, a terminal, and a network-side device are provided. The transmission processing method in embodiments of this application includes: acquiring, by a terminal, configuration information of a wake-up signal; and within a first time period, monitoring, based on the configuration information, the wake-up signal by the terminal, where the first time period is a time period in which first-physical-downlink-control-channel PDCCH monitoring is skipped; where the configuration information includes at least one of the following: wake-up signal type; transmission configuration; monitoring start time point; monitoring duration; monitoring occasion; and monitoring period.

Abstract: A method for learned image compression is provided. The method may include receiving first image data; downsampling the first image data to second image data; encoding the second image data to third image data, the third image data being a bitstream; decoding the third image data to fourth image data; and reconstructing, as reconstructed image data, the first image data based at least in part on the fourth image data and a feature vector.

Abstract: A method of task-adaptive pre-processing (TAPP) for neural image compression is performed by at least one processor and includes generating a substitutional image, based on an input image, using a TAPP neural network, and encoding the generated substitutional image to generate a compressed representation, using a first neural network.

Abstract: A memory device includes transistor structures and memory arc wall structures. The memory arc wall structures are embedded in the transistor structures. The transistor structure includes a dielectric column, a source electrode and a drain electrode, a gate electrode layer and a channel wall structure. The source electrode and the drain electrode are located on opposite sides of the dielectric column. The gate electrode layer is around the dielectric column, the source electrode, and the drain electrode. The channel wall structure is extended from the source electrode to the drain electrode and surrounds the dielectric column. The channel wall structure is disposed between the gate electrode layer and the source electrode, between the gate electrode layer, and the drain electrode, and between the gate electrode layer and the dielectric column. The memory arc wall structure is extended on and throughout the channel wall structure.

Abstract: A method for extracting a kansei adjective of a product based on principal component analysis and explanation (PCA-E) includes constructing a product kansei evaluation vector matrix through original kansei adjectives; performing dimensionality reduction through PCA; and determining, based on principal component load factors, kansei adjectives representing principal components. In this way, the kansei adjectives extracted are explanatory to help users understand the selected kansei adjectives and make accurate evaluation.

Abstract: A method of three-dimensional (3D)-Tree coding for neural network model compression, is performed by at least one processor, and includes reshaping a four-dimensional (4D) parameter tensor of a neural network into a 3D parameter tensor of the neural network, the 3D parameter tensor comprising a convolution kernel size, an input feature size, and an output feature size, partitioning the 3D parameter tensor along a plane that is formed by the input feature size and the output feature size into 3D coding tree units (CTU3Ds), partitioning each of the CTU3Ds into a plurality of 3D coding units (CU3Ds) recursively until a predetermined depth, using a quad-tree, and constructing a 3D tree for each of the plurality of CU3Ds, wherein the 3D tree for each of the plurality of CU3Ds is a 3D-Unitree.

Abstract: Disclosed are an intelligent power module and a manufacturing method thereof, which relate to the technical field of electronic devices. The intelligent power module includes a substrate, wherein a chip and a plurality of conductive pins are arranged on the substrate, one end of each of the conductive pins is connected to the chip, and a solder pin is formed at an end portion of the other end of the conductive pin; and an external pin frame, including a plurality of leads, and a connection structure is formed at an end portion of one end of each of the lead; and the connection structure includes a connection portion, and support portions, wherein an arrangement direction of the support portions is the same as that of the solder pins, an accommodation space is formed between the two support portions, and the solder pin is located between the two support portions.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode. The source region and the drain region are respectively disposed on two opposite ends of the insulating layer. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The interfacial layer is sandwiched between the channel layer and the ferroelectric layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: Systems, apparatus and methods are provided for low temperature management of a storage system. An apparatus may include a temperature sensor to generate a temperature reading, a timer configured with a time interval, a backup battery, one or more non-volatile memory (NVM) devices and a storage controller. The storage controller may be configured to: maintain a standby mode for low temperature management until a host electronic system has been turned off, start the timer and check the temperature reading when the host electronic system is turned off, determine that the temperature reading is below a temperature threshold, set the time interval based on the temperature reading, receive an interrupt from the timer when the timer counts to the time Interval, and perform low-temperature management operations for data stored in the one or more NVM devices using power supplied by the backup battery.

Abstract: Embodiments relates to a layout structure and a method for fabricating the same. A frequency divider pattern layer includes a first frequency divider region, a second frequency divider region, a third frequency divider region and a fourth frequency divider region arranged centrosymmetrically. A conductor pattern layer includes a first sub-conductor pattern layer and a second sub-conductor pattern layer stacked. The first sub-conductor pattern layer is configured to communicate the first frequency divider region with the second frequency divider region, and communicate the third frequency divider region with the fourth frequency divider region. The second sub-conductor pattern layer is configured to communicate the first frequency divider region with the fourth frequency divider region, and communicate the second frequency divider region with the third frequency divider region. The embodiments reduce a channel transmission difference between different frequency dividers in a frequency divider structure.

Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout comprising a cell and a layout context in a vicinity of the cell; receiving from a library a set of context groups and a set of timing tables, wherein each of the context groups is associated with one of the set of timing tables; determining a representative context group for the cell through comparing the layout context of the cell with the set of context groups; and performing a timing analysis on the layout according to a representative timing table associated with the representative context group for the cell.

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.

Abstract: A delivery apparatus includes a sheath assembly, a tip, and a handle assembly. The sheath assembly includes an inner core tube, a push tube surrounding and receiving the inner core tube, and a sheath surrounding and receiving the push tube and capable of moving axially relative to the push tube. The tip is connected to the distal end of the inner core tube. The handle assembly is connected to the proximal end of the sheath. A tube cavity channel for the inner core tube to extend through is provided within the push tube. A guide wire channel also is provided in the push tube. A limiting mechanism is provided on the tip and is used for being detachably connected to a guide wire extending through the guide wire channel.

Abstract: A storage system configured for use with an energy management system is provided and includes an AC rechargeable battery and a power converter operably coupled to the AC rechargeable battery and configured to calculate an estimate of state-of-charge of the AC rechargeable battery based on at least one of DC impedance of the AC rechargeable battery or AC impedance of the AC rechargeable battery that are measured in real time operation is used to calculate resistance and capacitance values for an equivalent circuit model that in conjunction with previously measured voltage and current are input to an extended kalman filter (EKF). Time consuming testing of the equivalent circuit model in advance is therefore eliminated.

Abstract: A method for extracting a kansei adjective of a product based on principal component analysis and explanation (PCA-E) includes constructing a product kansei evaluation vector matrix through original kansei adjectives; performing dimensionality reduction through PCA; and determining, based on principal component load factors, kansei adjectives representing principal components. In this way, the kansei adjectives extracted are explanatory to help users understand the selected kansei adjectives and make accurate evaluation.

Abstract: Aspects of the disclosure provide a method and an apparatus for video encoding. The apparatus includes processing circuitry configured to perform an iterative update of sample values of a plurality of samples in an initial input image. The iterative update includes generating a coded representation of a final input image based on the final input image by an encoding neural network (NN) and at least one training module. The final input image has been updated from the initial input image by a number of iterations of the iterative update. The iterative update includes generating a reconstructed image of the final input image based on the coded representation of the final input image by a decoding NN. One of a rate-distortion loss for the final input image or the number of iterations of the iterative update satisfies a pre-determined condition. An encoded image corresponding to the final input image is generated.

Abstract: A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.

Abstract: A package structure includes an isolation layer with multiple vias, N first pads, N Redistribution Layers (RDLs), and a first insulating layer. Each via exposes a respective part of an interconnection layer arranged on a surface of a semiconductor functional structure. Each first pad is formed by a respective part of the interconnection layer exposed by the corresponding via, N is a positive integer greater than 1. Each RDL covers the isolation layer and is electrically connected to a corresponding one of the N first pads. The first insulating layer is formed on the RDLs and exposes a part area of each RDL. The exposed part areas of at least some of the RDLs includes second pads and third pads. The center point of each second pad has the same offset direction and the same offset distance with respect to the center point of the corresponding first pad.