Abstract: A hollow-core optical fiber may include a substrate having a tubular shape and an inner surface surrounding a central longitudinal axis of the hollow-core optical fiber; a hollow core extending through the substrate along the central longitudinal axis of the hollow-core optical fiber; and a plurality of cladding elements positioned between the central longitudinal axis of the hollow-core optical fiber and the substrate. Each of the plurality of cladding elements may extend in a direction parallel to the central longitudinal axis of the hollow-core optical fiber. Each of the plurality of cladding elements may include a wound glass sheet configured as a spiral, and each of the plurality of cladding elements may contact an interior surface of the substrate.

Abstract: A hollow-core optical fiber may include a hollow core extending along a central longitudinal axis of the fiber; a substrate, the substrate having a tubular shape and an inner surface surrounding the central longitudinal axis of the fiber; and a plurality of cladding elements positioned between the hollow core and the substrate, each of the cladding elements extending in a direction parallel to the central longitudinal axis of the fiber. Each of the cladding elements includes a primary capillary, the primary capillary directly contacting the inner surface of the substrate and having an inner surface defining a cavity, and a plurality of nested capillaries positioned within the cavity, each of the nested capillaries directly contacting the inner surface of the primary capillary.

Abstract: A transmission processing method includes a first communications device sending transmission assistance information of first data, or discarding the first data according to transmission configuration information. The transmission assistance information is used for assisting a second communications device to execute transmission processing of the first data.

Abstract: A method for producing a hollow-core preform may include rolling a glass sheet to form a rolled-glass structure; and attaching one or more of the rolled-glass structures to an inner surface of an annular support structure to form a hollow-core preform, wherein the inner surface of the annular support structure defines an interior cavity and the one or more of the rolled-glass structures are positioned within the interior cavity. The hollow-core preform may be drawn into a hollow-core optical fiber.

Abstract: Aspects of the disclosure provide a method, an apparatus, and a non-transitory computer-readable storage medium for video decoding. The apparatus can include processing circuitry. The processing circuitry is configured to decode first neural network update information in a coded bitstream for a first neural network in the video decoder. The first neural network is configured with first pretrained parameters. The first neural network update information corresponds to a first block in an image to be reconstructed and indicates a first replacement parameter corresponding to a first pretrained parameter in the first pretrained parameters. The processing circuitry is configured to update the first neural network in the video decoder based on the first replacement parameter. The processing circuitry can decode the first block based on the updated first neural network for the first block.

Abstract: Systems, apparatus and methods are provided for temperature assisted non-volatile storage device management in a non-volatile storage system. In one embodiment, a non-volatile storage system may comprise a temperature sensor, a non-volatile storage device and a processor. The processor may be configured to obtain a read-out from the temperature sensor, generate a predicted real-time on-die temperature for the non-volatile storage device based on the read-out, generate an estimated threshold voltage for reading data stored in the non-volatile storage device based on the predicted real-time on-die temperature and conduct a local sweep of a reference voltage using the estimated threshold voltage as a starting point to obtain a final read reference voltage with a minimum read bit error rate.

Abstract: Provided are an Electro Static Discharge (ESD) circuit and a memory. The ESD circuit includes: a detection circuit and multiple electrostatic discharge circuits. The detection circuit includes at least one sub-detection circuit connected between a first power end and a second power end. Each sub-detection circuit generates a sub-trigger signal based on a voltage change between the first power end and the second power end. The multiple electrostatic discharge circuits are connected between the first power end and the second power end. The multiple electrostatic discharge circuits are configured to be turned on according to the one or more sub-trigger signals.

Abstract: An Online Meta Learning (“OML”) framework is provided for learned image compression (“LIC”) based on a variable-rate Conditional Variational Auto-Encoder (“CVAE”) architecture. A computing system is configured to learn, from multiple training tasks of compression with different RD tradeoff ?s, a set of task-general meta parameters controlled by meta-control variables ?. Meta parameters learn a mapping between the meta-control variables ? and compression effects of different RD tradeoffs ?s. Meta-control variables ? are adaptively determined and transmitted on the fly to an encoder and a decoder of an image compression process, to accommodate the current compression need for any current test datum. A parallelized context computation method is also provided for an online CVAE-based meta-LIC architecture; since OML requires multiple iterations at an encoder, parallel context estimation substantially improves computational time in practice.

Abstract: A system may receive an input image block, and input the input image block into multiple models which may be trained using a plurality of different datasets of image blocks. Each model of the multiple models may be trained using a dataset having similar attributes. The system may determine a model having a highest compression efficiency from among the multiple models, and encode the input image block using the determined model.

Abstract: A transmission processing method, a terminal, and a network-side device are provided. The transmission processing method in embodiments of this application includes: acquiring, by a terminal, configuration information of a wake-up signal; and within a first time period, monitoring, based on the configuration information, the wake-up signal by the terminal, where the first time period is a time period in which first-physical-downlink-control-channel PDCCH monitoring is skipped; where the configuration information includes at least one of the following: wake-up signal type; transmission configuration; monitoring start time point; monitoring duration; monitoring occasion; and monitoring period.

Abstract: A method for learned image compression is provided. The method may include receiving first image data; downsampling the first image data to second image data; encoding the second image data to third image data, the third image data being a bitstream; decoding the third image data to fourth image data; and reconstructing, as reconstructed image data, the first image data based at least in part on the fourth image data and a feature vector.

Abstract: A method of task-adaptive pre-processing (TAPP) for neural image compression is performed by at least one processor and includes generating a substitutional image, based on an input image, using a TAPP neural network, and encoding the generated substitutional image to generate a compressed representation, using a first neural network.

Abstract: A memory device includes transistor structures and memory arc wall structures. The memory arc wall structures are embedded in the transistor structures. The transistor structure includes a dielectric column, a source electrode and a drain electrode, a gate electrode layer and a channel wall structure. The source electrode and the drain electrode are located on opposite sides of the dielectric column. The gate electrode layer is around the dielectric column, the source electrode, and the drain electrode. The channel wall structure is extended from the source electrode to the drain electrode and surrounds the dielectric column. The channel wall structure is disposed between the gate electrode layer and the source electrode, between the gate electrode layer, and the drain electrode, and between the gate electrode layer and the dielectric column. The memory arc wall structure is extended on and throughout the channel wall structure.

Abstract: A method for extracting a kansei adjective of a product based on principal component analysis and explanation (PCA-E) includes constructing a product kansei evaluation vector matrix through original kansei adjectives; performing dimensionality reduction through PCA; and determining, based on principal component load factors, kansei adjectives representing principal components. In this way, the kansei adjectives extracted are explanatory to help users understand the selected kansei adjectives and make accurate evaluation.

Abstract: A method of three-dimensional (3D)-Tree coding for neural network model compression, is performed by at least one processor, and includes reshaping a four-dimensional (4D) parameter tensor of a neural network into a 3D parameter tensor of the neural network, the 3D parameter tensor comprising a convolution kernel size, an input feature size, and an output feature size, partitioning the 3D parameter tensor along a plane that is formed by the input feature size and the output feature size into 3D coding tree units (CTU3Ds), partitioning each of the CTU3Ds into a plurality of 3D coding units (CU3Ds) recursively until a predetermined depth, using a quad-tree, and constructing a 3D tree for each of the plurality of CU3Ds, wherein the 3D tree for each of the plurality of CU3Ds is a 3D-Unitree.

Abstract: Disclosed are an intelligent power module and a manufacturing method thereof, which relate to the technical field of electronic devices. The intelligent power module includes a substrate, wherein a chip and a plurality of conductive pins are arranged on the substrate, one end of each of the conductive pins is connected to the chip, and a solder pin is formed at an end portion of the other end of the conductive pin; and an external pin frame, including a plurality of leads, and a connection structure is formed at an end portion of one end of each of the lead; and the connection structure includes a connection portion, and support portions, wherein an arrangement direction of the support portions is the same as that of the solder pins, an accommodation space is formed between the two support portions, and the solder pin is located between the two support portions.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode. The source region and the drain region are respectively disposed on two opposite ends of the insulating layer. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The interfacial layer is sandwiched between the channel layer and the ferroelectric layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: Systems, apparatus and methods are provided for low temperature management of a storage system. An apparatus may include a temperature sensor to generate a temperature reading, a timer configured with a time interval, a backup battery, one or more non-volatile memory (NVM) devices and a storage controller. The storage controller may be configured to: maintain a standby mode for low temperature management until a host electronic system has been turned off, start the timer and check the temperature reading when the host electronic system is turned off, determine that the temperature reading is below a temperature threshold, set the time interval based on the temperature reading, receive an interrupt from the timer when the timer counts to the time Interval, and perform low-temperature management operations for data stored in the one or more NVM devices using power supplied by the backup battery.

Abstract: Embodiments relates to a layout structure and a method for fabricating the same. A frequency divider pattern layer includes a first frequency divider region, a second frequency divider region, a third frequency divider region and a fourth frequency divider region arranged centrosymmetrically. A conductor pattern layer includes a first sub-conductor pattern layer and a second sub-conductor pattern layer stacked. The first sub-conductor pattern layer is configured to communicate the first frequency divider region with the second frequency divider region, and communicate the third frequency divider region with the fourth frequency divider region. The second sub-conductor pattern layer is configured to communicate the first frequency divider region with the fourth frequency divider region, and communicate the second frequency divider region with the third frequency divider region. The embodiments reduce a channel transmission difference between different frequency dividers in a frequency divider structure.

Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout comprising a cell and a layout context in a vicinity of the cell; receiving from a library a set of context groups and a set of timing tables, wherein each of the context groups is associated with one of the set of timing tables; determining a representative context group for the cell through comparing the layout context of the cell with the set of context groups; and performing a timing analysis on the layout according to a representative timing table associated with the representative context group for the cell.