Abstract: A composite includes a substrate and a target material, wherein the target material includes indium oxide (In2O3), tin oxide (SnO2), and gallium oxide (Ga2O3), and a method for making the same. The method includes positioning the substrate and a target in a chamber and applying radio frequency (RF) power to the chamber to sputter ions of target material from the target onto the substrate.

Abstract: Provided are a method and device employing a smart contract to realize identity-based key management. The method comprises: running a smart contract, and executing a key management process, wherein the key management process comprises: when a key of a target user requires an update and the target user is not a supervised user, generating a master public key and a master private key pertaining to the target user; acquiring, from a blockchain, identity information of the target user; generating a first target private key according to the master public key and the master private key pertaining to the target user and the identity information of the target user; and replacing a current private key of the target user with the first target private key.

Abstract: In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.

Abstract: A data buffer circuit structure, a layout structure of multiple data buffer circuits, and a memory. The data buffer circuit structure includes a first amplification circuit, a second amplification circuit, a decision equalizer, and a power module. An output terminal of the first amplification circuit, an input terminal of the second amplification circuit, and adjustment output terminals of the decision equalizer are connected through a signal line. The power module includes a first power supply unit and a second power supply unit. A minimum distance between the first power supply unit and the first amplification circuit is less than a minimum distance between the first power supply unit and the second amplification circuit, and a minimum distance between the second power supply unit and the second amplification circuit is less than a minimum distance between the second power supply unit and the first amplification circuit.

Abstract: The present application provides a three-dimensional object printing method and device, and a three-dimensional printing material, where the printing method includes: forming a powder material layer by using a powder material, where the powder material layer includes a molding area and a non-molding area; spraying a first liquid material and a second liquid material at a first ratio in the molding area of the powder material layer according to layer printing data, where the second liquid material promotes a polymerization reaction of the first liquid material to form a layer solid portion of a three-dimensional object; and spraying the first liquid material and the second liquid material at a second ratio in the non-molding area of the powder material layer according to the layer printing data to form a layer protective portion of the three-dimensional object, where the first ratio is greater than the second ratio.

Abstract: The present application relates to a technical field of plastic article, and in particular, to a degradable plastic bottle, a preparation method therefor and a degradation method therefor. The bottle is prepared by blowing a combined degradable material formed by melting and extruding a resin mixture, the resin mixture includes the following components in parts by weight: 10-60 parts of polylactic acid, 20-50 parts of polybutylene adipate terephthalate, 0.5-20 parts of polymethyl ethylene carbonate, 0.5-20 parts of polyglycolic acid, and 1-10 parts of calcium carbonate.

Abstract: A method, computer program, and computer system is provided for compressing a neural network model. One or more indices corresponding to a multi-dimensional tensor associated with a neural network are reordered. A set of weight coefficients associated with the one or more reordered indices is unified. A model of the neural network is compressed based on the unified set of weight coefficients.

Abstract: A method and an apparatus for sorting and identifying single cells. The method includes a liquid supplying step, first nozzle imaging and recognizing step, single cell printing and imaging step, and second nozzle imaging step. The present disclosure adopts a high-throughput microfluidic design of thermal bubble printing chip and image recognition, which can expel the single cells gently and efficiently, thereby obtaining a high volume of single cells with high single cell yield and high single cell activity quickly. The method recognizes single cells based on cellular morphological features, facilitating obtaining single cells with high activity. Furthermore, the method provides the appearance of single cells on day zero, an important criterion for single cell analysis. The apparatus of the present disclosure provides a comprehensive solution for cellular experiments by monitoring the cell growth and locating the target cells based on fluorescent markers after single cell sorting.

Abstract: The present disclosure includes a method, apparatus, and non-transitory computer-readable medium for adaptive neural image compression by meta-learning. The method may include generating a substitute input image and a substitute target quality control parameter using an original input image and a target quality control parameter, wherein the substitute input image is a modified version of the original input image and the substitute target quality control parameter is a modified version of the target quality control parameter. The method may further include encoding the substitute input image, based on the substitute input image and the substitute target quality control parameter, using an encoding neural network, to generate a compressed representation of the substitute input image.

Abstract: A toner cartridge is disclosed. A hole and a window are disposed on two sides of a cartridge body separately. A toner hopper is disposed in the cartridge body, and is configured to accommodate toner, and a supply opening exposed in the window is disposed at a position that is on the toner hopper and that faces the window. The first agitator is disposed in the toner hopper, and is configured to transport the toner in the toner hopper to the supply opening. A first hopper door is slidably disposed on a side that is of the toner hopper and that faces the window, a slot is disposed on the first hopper door, and the first hopper door may open or close the supply opening when sliding. The first clamping hook is disposed on the second side of the cartridge body.

Abstract: A semiconductor memory device includes a substrate, a stack structure disposed on the substrate, a plurality of dielectric isolation segments extending through the stack structure, and a plurality of memory cell structures. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers alternatingly stacked in a Z direction substantially perpendicular to the substrate. The memory cell structures are disposed in the stack structure, and are separated from one another by the dielectric isolation segments. Each of the memory cell structures includes a pair of conductive segments each penetrating the stack structure in the Z direction, a dielectric separation segment separating the conductive segments, a conductive channel segment enclosing side surfaces of the conductive segments and the dielectric separation segment, and a memory segment enclosing side surface of the conductive channel segment and being connected between the stack structure and the conductive segment.

Abstract: A manufacturing method of a transistor includes at least the following steps. An insulating layer is provided. A source/drain material layer is formed on the insulating layer to cover top surface and sidewalls of the insulating layer. A portion of the source/drain material layer is removed until the insulating layer is exposed, so as to form a source region and a drain region respectively on two opposite sidewalls of the insulating layer. A channel layer is deposited on the insulating layer, the source region, and the drain region. A ferroelectric layer is formed over the channel layer through a non-plasma deposition process. A gate electrode is formed on the ferroelectric layer. The gate electrode, the ferroelectric layer, and the channel layer are patterned to expose at least a portion of the insulating layer, at least a portion of the source region, and at least a portion of the drain region.

Abstract: A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.

Abstract: The present disclosure relates to a touch-sensitive key protective film, a mobile phone shell, and a protective film sticking device. The touch-sensitive key protective film is stuck to an end face of a touch-sensitive key disposed on a side edge of the mobile phone. The touch-sensitive key protective film is an obround membrane, including a conductive adhesive layer, an explosion-proof film layer, a glass layer, and an oil-resistant layer that are sequentially arranged, where the conductive adhesive layer is bonded to the end face of the touch-sensitive key disposed on the side edge of the mobile phone, a thickness of the explosion-proof film layer is 0.08-0.12 mm, and the thickness of the glass layer is 0.18-0.22 mm. The touch-sensitive key protective film is bonded to the touch-sensitive key disposed on the side edge of the mobile phone through the conductive adhesive.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

Abstract: In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.

Abstract: A semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. The structure also includes a source structure and a drain structure formed over the channel layer. The structure further includes a first isolation structure formed between the source structure and the drain structure. The source structure extends over the cap layer and towards the drain structure.

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

Abstract: A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.

Abstract: A device includes a first conductive line as an input line. The device further includes a second conductive line as an output line, wherein the first conductive line and the second conductive line are in a same level of the integrated circuit. The device further includes a first passive isolation structure between the first conductive line and the second conductive line, wherein the first passive isolation structure and the second conductive line are each positioned at an integer multiple of an interval between the first conductive line and the first passive isolation structure.