Abstract: Systems and methods for automatically inserting advertisements into source video content playback streams are described. In one aspect, the systems and methods communicate a source video content playback stream to a video player to present source video to a user. During playback of the source video, and in response to receipt of a request from the user to navigate portions of the source video (e.g., a user command to fast forward the source video, rewind the source video, or other action), the systems and methods dynamically define a video advertisement clip insertion point (e.g., and insertion point based on a current playback position). The systems and methods then insert a contextually relevant and/or targeted video advertisement clip into the playback stream for presentation to the user.

Abstract: A test device uses a single probe to test plurality of pads of at least one chip, and includes a test circuit, a plurality of short-circuit elements and a plurality of probes. The plurality of short-circuit elements is formed in scribe lines around the at least one chip, where each of the plurality of short-circuit elements connects the plurality of pads, and the plurality of pads includes one testing pad and at least one non-testing pad. The plurality of probes receives a plurality of test signals generated by the at least one chip from the testing pad via the plurality of short-circuit elements, so the test circuit generates a test result according to the plurality of test signals.

Abstract: Embodiments of the present invention relate to a method for a near non-adaptive virtual metrology for wafer processing control. In accordance with an embodiment of the present invention, a method for processing control comprises diagnosing a chamber of a processing tool that processes a wafer to identify a key chamber parameter, and controlling the chamber based on the key chamber parameter if the key chamber parameter can be controlled, or compensating a prediction model by changing to a secondary prediction model if the key chamber parameter cannot be sufficiently controlled.

Abstract: Solid forms comprising N-(5-tert-butyl-isoxazol-3-yl)-N?-{4-[7-(2-morpholin-4-yl-ethoxy)imidazo[2,1-b][1,3]benzothiazol-2-yl]phenyl}urea, compositions comprising the solid forms, methods of making the solid forms and methods of their use for the treatment of various diseases and/or disorders are disclosed.

Abstract: A Co3W3C fishbone-like hard phase-reinforced Fe-based wear-resistant coating and the preparation thereof, which belongs to the field of a wear-resistant coating on the surface of a material and a preparation method thereof. The wear-resistant coating comprises: 1.89-3.77% of C, 5.4-11.7% of Cr, 3.3-7.15% of Ni, 28.81-57.83% of W, 4.2-8.4% of Co, 0.03-0.065% of Si and the balance of Fe. The preparation process of the wear-resistant coating comprises: (1) before plasma cladding, pretreating a matrix; (2) pretreating an iron-based alloy powder; and (3) adjusting the process parameters of plasma cladding, preparing a cladding layer with a predetermined width and a predetermined thickness, and naturally cooling same down in air.

Abstract: Systems and methods for automatically inserting advertisements into source video content playback streams are described. In one aspect, the systems and methods communicate a source video content playback stream to a video player to present source video to a user. During playback of the source video, and in response to receipt of a request from the user to navigate portions of the source video (e.g., a user command to fast forward the source video, rewind the source video, or other action), the systems and methods dynamically define a video advertisement clip insertion point (e.g., and insertion point based on a current playback position). The systems and methods then insert a contextually relevant and/or targeted video advertisement clip into the playback stream for presentation to the user.

Abstract: A data storage device including a flash memory and a controller. The flash memory includes a plurality of blocks, and each of the blocks has a plurality of pages. The controller receives a write command which is arranged to write a plurality of data sectors into a plurality of first pages of a first block of the blocks, calculates an offset index according to a first erase count of the first block, retrieving a plurality of seeds from a random seed table according to the offset index, encodes the data sectors by using the retrieved seeds to obtain a plurality of encoded data sectors, and writes the encoded data sectors into the first pages.

Abstract: An electrostatic discharge protection device including a silicon controlled rectifier. In one example, the silicon controlled rectifier includes a first n-type region located in a semiconductor substrate. The silicon controlled rectifier also includes a first p-type region located adjacent the first n-type region in the semiconductor substrate. The silicon controlled rectifier further includes an n-type contact region and a p-type contact region located in the first n-type region. The silicon controlled rectifier also includes an n-type contact region and a p-type contact region located in the first p-type region. The silicon controlled rectifier further includes a blocking region having a higher resistivity than the first p-type region. The blocking region is located between the n-type contact region and the p-type contact region in the first p-type region for reducing a trigger voltage of the silicon controlled rectifier.

Abstract: Embodiments of a method for providing electrostatic discharge (ESD) protection for an Input/Output (I/O) device, an ESD protection device for an I/O device, and an I/O device are described. In one embodiment, a method for providing ESD protection for an I/O device involves activating a switch device to turn off the I/O device during an ESD event and deactivating the switch device to turn on the I/O device in the absence of an ESD event. Other embodiments are also described.

Abstract: A system for displaying images is provided. The system includes a touch sensor device including a transparent substrate having a sensing region and a non-sensing region adjacent to the sensing region. A sensing electrode pattern layer is on the transparent substrate in the sensing region. An inorganic dielectric material layer is on the transparent substrate. The inorganic dielectric material layer has a first portion in the non-sensing region and a second portion in the sensing region and partially covering the sensing electrode pattern layer. A method of forming a touch sensor device is also disclosed.

Abstract: A telescopic locating structure includes a linearly extending first extension member and a linearly extending second extension member. The second extension member is coaxially slidably fitted and connected with the first extension member. The second extension member s coaxially reciprocally telescopically moved relative to the first extension member. The telescopic locating structure further includes a second connection member having an engagement section slidably disposed on the second extension member. The geometrical central axis of the engagement section is eccentric to the axis of the second extension member. Accordingly, the engagement section can be engaged between the second extension member and other fixing member so as to restrict and locate the second extension member.

Abstract: An electrostatic discharge power rail clamp circuit and an integrated circuit including the same. The power rail clamp circuit includes a first power rail, a second power rail and a first node. The circuit further includes an n-channel field effect transistor having a source and drain located in an isolated p-well in a semiconductor substrate. The drain is connected to the first power rail. The source and isolated p-well are connected to the first node. The circuit also includes a capacitor connected between the first node and the second power rail. The circuit further includes a resistor connected between the first power rail and the first node. The circuit also includes an inverter for controlling the gate of the field effect transistor, wherein the inverter has an input connected to the first node. The circuit further a silicon controlled rectifier connected between the first node and the second power rail.

Abstract: An ESD protection device for shunting an electrostatic discharge current from a first node to a second node, and an integrated circuit including the same. The device includes a first bipolar transistor having a collector and an emitter located in a first n-type region. The emitter of the first transistor is connected to the first node. The device also includes a second bipolar transistor having a collector and an emitter located in a second n-type region. The emitter of the second transistor is connected to the collector of the first bipolar transistor. The device further includes a pn junction diode including a p-type region located in a third n-type region. The p-type region of the diode is connected to the collector of the second bipolar transistor and the third n-type region is connected to the second node.

Abstract: An active probe card capable of improving testing bandwidth of a device under (DUT) test includes a printed circuit board; at least one probe needle, affixed to a first surface of the printed circuit board for probing the DUT; at least one connection member, electrically connected to the at least one probe needle; and an amplification circuit, formed on the printed circuit board and coupled to the at least one connection member for amplifying an input or output signal of the DUT.

Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

Abstract: An integrated circuit memory includes a memory array, including a plurality of data lines. A buffer structure is coupled to the plurality of data lines, including a plurality of storage elements to store bit-level status values for the plurality of data lines. The memory includes logic to indicate bundle-level status values of corresponding bundles of storage elements in the buffer structure based on the bit-level status values of bits in the corresponding bundles. A plurality of bundle status circuits is arranged in a daisy chain and coupled to respective bundles in the buffer structure, producing an output of the daisy chain indicating detection of a bundle in the first status. Control circuitry executes cycles to determine the output of the daisy chain, each cycle clearing a bundle status circuit indicating the first status if the output indicates detection of a bundle in the first status in the cycle.

Abstract: A display panel including a plurality of pixel units is provided. Each pixel unit includes a first substrate, a second substrate and a display media therebetween. The first substrate includes a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel. The first sub-pixel includes a first active device and a first pixel electrode electrically connected to the first active device, wherein the first pixel electrode has a first main slit and a plurality of first branch slits connected thereto. The second sub-pixel includes a second active device and a second pixel electrode electrically connected to the second active device, wherein the second pixel electrode has a second main slit and a plurality of second branch slits connected thereto. The second substrate includes a first electrode pattern and a second electrode pattern respectively corresponding to the first pixel electrode and the second pixel electrode, and a connecting portion therebetween.

Abstract: An integrated circuit (IC) testing interface capable of upgrading an automatic test equipment (ATE) for testing a semiconductor device includes at least one pin for receiving or transmitting at least a test signal to a tester of the automatic test equipment, a plurality of digitizers coupled to the at least one pin for generating a digital signal, a processing means coupled to the plurality of digitizers for processing the digital signal, and a connection unit for connecting the processing means with a computing device for transmitting an output signal from the processing means to the computing device, where the IC testing interface is disposed between the tester and a prober of the automatic test equipment.

Abstract: A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

Abstract: A semiconductor device and method. The device includes a first domain and a second domain each having a power rail and a ground rail. The device further includes a signal line connected between the first domain and the second domain. The device also includes an electrostatic discharge protection circuit for providing cross-domain ESD protection. The protection circuit includes a blocking transistor connected between the first domain power rail and the signal line. The protection circuit also includes a power rail clamp connected between the first domain power rail and the first domain ground rail. The power rail clamp is operable to apply a control signal to a gate of the blocking transistor to switch it on during normal operation and to switch it off during an ESD event. The power rail clamp is operable during the ESD event to conduct an ESD current.