Abstract: An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current pulse from the input pad to the output pad.

Abstract: An integrated circuit structure includes a substrate having a front side and a back side, the back side being an opposite side of the substrate from the front side. A first power rail extends in a first direction, is embedded in the front side of the substrate, and provides a first supply voltage. A second power rail provides a second supply voltage different from the first supply voltage, extends in the first direction, is embedded in the front side of the substrate, and is separated from the first power rail in a second direction different from the first direction. A first device is positioned between the first power rail and the second power rail and located on the front side of the substrate. A first via structure extends to the back side of the substrate and is electrically coupled to the second power rail.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a first bipolar device connected to a first node, a second bipolar device connected to the first bipolar device and to a second node, and a metal-oxide-semiconductor (MOS) device connected to the first and second nodes and to the first and second bipolar devices and configured to shunt current in response to an ESD pulse received between the first and second nodes. The first bipolar device, the second bipolar device, and the MOS device are formed on a deep well structure. Other embodiments are also described.

Abstract: A display device having a display region and a peripheral region surrounding the display region is provided. The display device includes a first adhesion layer sandwiched between a display unit and a protective structure. The protective structure includes a first protective layer having a first length in a first direction. The protective structure also includes a second adhesion layer disposed on the first protective layer. The protective structure further includes a second protective layer disposed on the second adhesion layer, and the second protective layer has a second length in the first direction, wherein the difference between the first length and the second length is between 0 and 1 mm, and wherein the second protective layer is on the outermost side of the display device.

Abstract: An imaging lens assembly includes a plurality of lens elements, wherein at least one of the lens elements is a dual molded lens element. The dual molded lens element includes a light transmitting portion and a light absorbing portion. The light transmitting portion includes an effective optical section. The light absorbing portion is located on at least one surface of an object-side surface and an image-side surface of the dual molded lens element, wherein a plastic material and a color of the light absorbing portion are different from a plastic material and a color of the light transmitting portion, and the light absorbing portion includes an opening. The opening is non-circular and disposed correspondingly to the effective optical section.

Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.

Abstract: An ESD circuit is connected with a pad. The ESD circuit includes a voltage divider, a RC circuit and a path control circuit. The voltage divider is connected between the pad and a first node and provides plural divided voltages. The RC circuit is connected between the pad and the first node. The RC circuit receives the plural divided voltages and provides a control circuit. The path control circuit is connected with the pad and the first node. The path control circuit receives the plural divided voltages and the control voltage. When the pad receives a first ESD zap, the RC circuit controls the path control circuit to turn on a first ESD current path. Consequently, an ESD current flows from the pad to the first node through the first ESD current path.

Abstract: A method of generating a layout diagram includes: identifying a first area in the layout diagram which is populated with cells, the first area including first and second rows extending substantially parallel to a first direction, the first and second rows having substantially different cell densities; relative to a second direction, substantially perpendicular to the first direction, the first and second rows having corresponding first (H1) and second (H2) heights; for a first one of the cells having H1 height (a first H1 cell) in a first location in the first row, substituting a multi-row-height cell for the first H1 cell, the multi-row-height cell being narrower than the first H1 cell relative to the first direction; and placing a first part of the multi-row-height cell into a portion of the first location resulting in the first and second rows having more similar cell densities.

Abstract: An imaging lens assembly includes a plurality of lens elements, wherein at least one of the lens elements is a dual molded lens element. The dual molded lens element includes a light transmitting portion and a light absorbing portion. The light transmitting portion includes an effective optical section and a first annular surface. The light absorbing portion is located on at least one surface of an object-side surface and an image-side surface of the dual molded lens element, wherein a plastic material and a color of the light absorbing portion are different from a plastic material and a color of the light transmitting portion, and the light absorbing portion includes an opening and a second annular surface. A step surface of the second annular surface is formed by the first annular surface and the second annular surface.

Abstract: An imaging lens assembly includes a plurality of lens elements, wherein at least one of the lens elements is a dual molded lens element. The dual molded lens element includes a light transmitting portion and a light absorbing portion. The light transmitting portion includes an effective optical section and a first annular surface. The light absorbing portion is located on at least one surface of an object-side surface and an image-side surface of the dual molded lens element, wherein a plastic material and a color of the light absorbing portion are different from a plastic material and a color of the light transmitting portion, and the light absorbing portion includes an opening and a second annular surface. A step surface of the second annular surface is formed by the first annular surface and the second annular surface.

Abstract: A method of modifying an integrated circuit includes operations related to identifying at least two fin-containing functional areas of the integrated circuit, generating a performance curve for each fin-containing functional area of the integrated circuit for each fin height of a series of fin heights, and determining whether an inflection point exists for each performance curve. The method further includes operations related to selecting a value of a performance characteristic for each of the fin-containing functional areas, the selected value having a corresponding fin height in each of the fin-containing functional areas, modifying each fin-containing functional area to have the fin height corresponding to the selected value of the performance characteristic; and combining the modified fin-containing functional areas to form a modified integrated circuit.

Abstract: A display device having a display region and a peripheral region surrounding the display region is provided. The display device includes a first adhesion layer sandwiched between a display unit and a protective structure. The protective structure includes a first protective layer having a first length in a first direction. The protective structure also includes a second adhesion layer disposed on the first protective layer. The protective structure further includes a second protective layer disposed on the second adhesion layer, and the second protective layer has a second length in the first direction, wherein the difference between the first length and the second length is between 0 and 1 mm, and wherein the second protective layer is on the outermost side of the display device.

Abstract: A defect displaying method is provided in the disclosure. The method comprises acquiring defect group information from an image of a wafer, wherein the defect group information includes a set of correlations between a plurality of defects identified from the image and one or more corresponding assigned defect types and displaying at least some of the plurality of defects according to their corresponding assigned defect types.

Abstract: A server for knowledge recommendation for defect review. The server includes a processor electronically coupled to an electronic storage device storing a plurality of knowledge files related to wafer defects. The processor is configured to execute a set of instruction to cause the server to: receive a request for knowledge recommendation for inspecting an inspection image from a defect classification server; search for a knowledge file in the electronic storage device that matches the inspection image; and transmit the search result to the defect classification server.

Abstract: Various embodiments are directed to electrostatic discharge (ESD) protection apparatus comprising a bipolar junction transistor (BJT) having terminals, a field-effect transistor (FET) having terminals, and a common base region connected to a recombination region. The BJT and the FET are integrated with one another and include a common region that is shared by the BJT and the FET. The BJT and FET collectively bias the common base region and prevent triggering of the BJT by causing a potential of the common base region to follow a potential of one of the terminals of the BJT in response to an excessive but tolerable non-ESD voltage change at one or more of the terminals.

Abstract: An electrostatic discharge protection device is provided. A voltage selection circuit selects a voltage having a higher voltage value among a reference voltage and a voltage on a conductive path and supply the selected voltage to a RC latch self-feedback circuit, so that the RC latch self-feedback circuit ties a voltage of an input end of a RC control circuit when the electrostatic discharge does not occur, and disconnect a switch that conducts an electrostatic current.

Abstract: An ESD circuit is connected to a power pad and a first node. The ESD circuit includes a RC circuit and a first ESD current path. The RC circuit is connected between the power pad and the first node. The RC circuit is capable of providing a first control voltage and a second control voltage. The first ESD current path is connected between the power pad and the first node. When the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage and the second control voltages provided by the RC circuit, so that an ESD current flows from the power pad to the first node through the first ESD current path.

Abstract: An imaging lens assembly includes a plurality of lens elements, wherein at least one of the lens elements is a dual molded lens element. The dual molded lens element includes a light transmitting portion and a light absorbing portion. The light transmitting portion includes an effective optical section and a first annular surface. The light absorbing portion is located on at least one surface of an object-side surface and an image-side surface of the dual molded lens element, wherein a plastic material and a color of the light absorbing portion are different from a plastic material and a color of the light transmitting portion, and the light absorbing portion includes an opening and a second annular surface. A step surface of the second annular surface is formed by the first annular surface and the second annular surface.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes three or more bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes and a diode connected in series with the three or more bipolar transistors and one of the first and second nodes. Each of the three or more bipolar transistors includes a collector comprising collector components, an emitter comprising emitter components, and a base structure comprising a substrate region or an active region. The emitter components are alternately located with respect to the collector components. The substrate region or the active region surrounds the collector components and the emitter components. Other embodiments are also described.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes stacked first and second PNP bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes and an NMOS transistor connected in series with the stacked first and second PNP bipolar transistors and the second node. An emitter and a base of the second PNP bipolar transistor are connected to a collector of the first PNP bipolar transistor. A gate terminal of the NMOS transistor is connected to a source terminal of the NMOS transistor. Other embodiments are also described.