Abstract: An integrated circuit includes a plurality of first layer deep lines and a plurality of first layer shallow lines. The integrated circuit also includes a plurality of second layer deep lines and a plurality of second layer shallow lines. Each of the first layer deep lines and the first layer shallow lines is in a first conductive layer. Each of the second layer deep lines and the second layer shallow lines is in a second conductive layer above the first conductive layer.

Abstract: A defect displaying method is provided in the disclosure. The method comprises acquiring defect group information from an image of a wafer, wherein the defect group information includes a set of correlations between a plurality of defects identified from the image and one or more corresponding assigned defect types and displaying at least some of the plurality of defects according to their corresponding assigned defect types.

Abstract: An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell.

Abstract: A method of manufacturing a semiconductor device that includes identifying a first area in the layout diagram which is populated with cells, the first area including first and second rows extending substantially parallel to a first direction, the first and second rows having substantially different cell densities; relative to a second direction, substantially perpendicular to the first direction, the first and second rows having corresponding first (H1) and second (H2) heights. The method also includes replacing cells in the first row which have the H1 height with corresponding substitute cells, each substitute cell being correspondingly taller relative to the second direction and correspondingly narrower relative to the first direction, the replacing thereby increasing a density of the second row at least without substantially increasing a density of the first row.

Abstract: A method includes: doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

Abstract: A semiconductor device and a method of manufacturing the device are disclosed. In one aspect, the semiconductor device includes a first active region that extends along a first lateral direction and includes a plurality of first epitaxial structures. The semiconductor device also includes an interconnect structure that also extends along the first lateral direction and is disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure. The interconnect structure includes at least a first portion that offsets from the first active region along a second lateral direction perpendicular to the first lateral direction.

Abstract: A contact lens includes a central region, an annular region and a peripheral region. The central region includes a central point of the contact lens. The annular region symmetrically surrounds the central region. The peripheral region symmetrically surrounds the annular region. The peripheral region includes at least one color pattern portion. The annular region includes at least one power of critical point.

Abstract: An integrated circuit includes a semiconductor substrate, transistors on the semiconductor, horizontal routing tracks extending in a first direction in a first metal layer, and one or more backside routing tracks extending in the first direction in a backside metal layer. Each transistor has a gate terminal, a source terminal, and a drain terminal. A first transistor has a first terminal, a second terminal, and a third terminal. A first horizontal routing track of the horizontal routing tracks is conductively connected to the first terminal of the first transistor through a via connector. A first backside routing track is conductively connected to the second terminal of the first transistor through a backside via connector. The backside metal layer and the first metal layer are formed at opposite sides of the semiconductor substrate.

Abstract: An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

Abstract: A contact lens includes a central region, an annular region and a peripheral region. The central region includes a central point of the contact lens. The annular region symmetrically surrounds the central region. The peripheral region symmetrically surrounds the annular region. The peripheral region includes at least one color pattern portion. The annular region includes at least one power of critical point.

Abstract: A modular connection device is provided. The modular connection device includes a base and a plurality of connection members. The base includes a plurality of connection surfaces, wherein each of the connection surfaces is connected with each other. Each of the connection members is detachably connected on each of the connection surfaces.

Abstract: The present disclosure provides a semiconductor structure, including a substrate, a first metal line over the substrate and extending along a first direction, a protection layer lining a sidewall of the first metal line, a second metal line above the first metal line and extending along the first direction, and a third metal line above the second metal line, extending along a second direction perpendicular to the first direction.

Abstract: A pneumatic ratchet wrench includes a main body formed with a receiving chamber, a head unit, a driving unit and an air motor. The head unit defines a gas passage, and includes a ring portion and a frame portion. The ring portion includes an exit in spatial communication with the gas passage and opens toward the frame portion. The driving unit includes a driving head, and a transmission shaft mounted in the head unit. The air motor drives the transmission shaft and includes a cylinder and a rotor. The cylinder includes a venting hole allowing gas produced in the cylinder to pass through the venting hole and the gas passage and to exit from the exit to be blown toward the frame portion.

Abstract: A pixel structure including a pixel electrode and an alignment electrode is provided. An outline of the pixel electrode is surrounded by first long and short sides, a second long side opposite to the first long side, and a second short side opposite to the first short side. The pixel electrode has a first opening, extending along the first long side, and a second opening, extending from the first opening toward the second long side. The first opening is narrower than the second opening. The alignment electrode is physically separated from the pixel electrode and includes a first extension portion adjacent to the second long side and two supplemental portions positioned at two ends of the first extension portion. The two supplemental portions both extend from the first extension portion toward the first long side and respectively along the first short side and the second short side.

Abstract: A pixel structure including a pixel electrode and an alignment electrode is provided. An outline of the pixel electrode is surrounded by first long and short sides, a second long side opposite to the first long side, and a second short side opposite to the first short side. The pixel electrode has a first opening, extending along the first long side, and a second opening, extending from the first opening toward the second long side. The first opening is narrower than the second opening. The alignment electrode is physically separated from the pixel electrode and includes a first extension portion adjacent to the second long side and two supplemental portions positioned at two ends of the first extension portion. The two supplemental portions both extend from the first extension portion toward the first long side and respectively along the first short side and the second short side.

Abstract: A method and a system for encryption and decryption based on continuous-variable quantum neural network CVQNN. The method includes: updating a weight of the CVQNN with a training sample; triggering, by a sender, a legal measurement bases synchronization between the sender and the CVQNN; converting, by the sender, the information to be sent into a quadratic plaintext according to the synchronized measurement bases, and sending the quadratic plaintext to the CVQNN; encrypting, by the CVQNN, a received quadratic plaintext, and sending an encrypted quadratic plaintext to a receiver; after receiving the encrypted quadratic plaintext, sending by the receiver the encrypted quadratic plaintext to the CVQNN for decryption to obtain decrypted information. The embodiments implement data encryption and decryption by introducing CVQNN model and synchronization measurement technology. The embodiments provide advantages of high reliability, high security and easy realization.

Abstract: An arrangement to guarantee boot up of a computer includes a control center microchip with BIOS boot block and BIOS program, and a flash memory divided into a first protected block, a main block, and a second protected block. In the computer, an embedded controller (EC) with stored modules is electrically connected to the flash memory and the control center microchip. The modules include a determining module to check that the code of the first protected block is identical with the code of the second protected block and a recovery module able to reinstate correct code from the second protected block into the first protected block if required. A method applied to the disclosed computer startup detection system is also disclosed.