Abstract: An imaging lens assembly includes a plurality of lens elements, wherein at least one of the lens elements is a dual molded lens element. The dual molded lens element includes a light transmitting portion and a light absorbing portion. The light transmitting portion includes an effective optical section. The light absorbing portion is located on at least one surface of an object-side surface and an image-side surface of the dual molded lens element, wherein a plastic material and a color of the light absorbing portion are different from a plastic material and a color of the light transmitting portion, and the light absorbing portion includes an opening. The opening is non-circular and disposed correspondingly to the effective optical section.

Abstract: A semiconductor device includes a first transistor having a first fin, wherein a base of the first fin is surrounded by a first dielectric material, the first fin having a first fin height measured from the top surface of the first dielectric material to a top surface of the first fin; and a second transistor having a second fin, wherein a base of the second fin is surrounded by a second dielectric material, the second fin having a second fin height measured from a top surface of the second dielectric material to a top surface of the second fin, wherein the first fin height is different from the second fin height.

Abstract: A locking assembly for a Kensington-locked enclosure can be simply padlocked for security. The locking assembly includes a first connecting member and a second connecting member. The first connecting member is fixed on a base body of the enclosure, the first connecting member comprises a first tongue piece. The second connecting member is fixed on an upper cover of the enclosure, and the second connecting member comprises a second tongue piece. The first tongue piece and the second tongue piece protrude from an outside of the enclosure and fit each other, and a padlock can pass through the first tongue piece and the second tongue piece to lock the base body and the upper cover together and secure the attachment of the Kensington lock.

Abstract: The present disclosure provides a fixing device for fixing an external electronic component on a motherboard in a chassis. The fixing device includes a fixing block and a telescopic block. The fixing block is fixed on the chassis. One end of the telescopic block is slidably mounted in the fixing block, the other end protrudes from the fixing block and holds the electronic component. A chassis including the above-described fixing device to hold electronic components of different sizes is also provided.

Abstract: For a mapping application, a method for reporting a problem related to a map displayed by the mapping application is described. The method identifies a mode in which the mapping application is operating. The method identifies a set of types of problems to report based on the identified mode. The method displays, in a display area of the mapping application, a graphical user interface (GUI) page that includes a set of selectable user interface (UI) items that represent the identified set of types of problems.

Abstract: A screwdriver includes a shank with a handle connected to a collar rotatably and a base is located in a room of the handle. At least one resilient extending from the underside of the collar is inserted in at least one recess of the handle. The base connected to the outside of the collar has a rod connected to a positioning member. The positioning member is defined with multiple slots able to hold bits in position in the room. One side of the base is sealed by a cap. Therefore, the bits are received inside of the handle so as to carry with the screwdriver.

Abstract: An electrostatic discharge protection device is provided. A voltage selection circuit selects a voltage having a higher voltage value among a reference voltage and a voltage on a conductive path and supply the selected voltage to a RC latch self-feedback circuit, so that the RC latch self-feedback circuit ties a voltage of an input end of a RC control circuit when the electrostatic discharge does not occur, and disconnect a switch that conducts an electrostatic current.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: An apparatus for use in a polar transmitter to perform distortion estimation and compensation is provided. The apparatus includes a mixing unit, a signal processing unit, an estimation unit and a compensation unit. The mixing unit is configured to mix a test output signal and a frequency down-converting signal to generate a mixed signal. The processing unit is configured to perform signal processing on the mixed signal to generate a processed signal. The estimation unit is configured to perform distortion estimation on the processed signal to generate a distortion estimation result. The compensation unit is configured to perform pre-distortion compensation on input signals of the polar transmitter according to the distortion estimation result.

Abstract: An electronic device includes a housing and a buffer component. The housing has a corner portion and two side edges adjacent to the corner portion. The buffer component is embedded in the corner portion and includes a strengthened layer and a buffer layer. The strengthened layer includes an arc-shaped side edge and an embedded portion. The embedded portion is embedded in the corner portion, such that the arc-shaped side edge is aligned with the two side edges. The strengthened layer is a strengthened material structure. The buffer layer is disposed between the strengthened layer and the housing, and the buffer layer is an elastic material structure.

Abstract: A multi-antenna system includes: a server; a first antenna group, provided on a base station and including multiple first antennas including a first representative antenna and a first non-representative antenna, the base station performing intra-group channel estimation to obtain and transmit to the server multiple first inner channel estimation coefficients between the first representative antenna and the first non-representative antenna, and serving a user device; and a reference device, communicating with the server and the first antennas, performing channel estimation between the reference device and the first representative antenna to obtain and transmit to the server multiple first outer channel estimation coefficients between the reference device and the first representative antenna. The server calculates a precoding matrix according to the first inner and first outer channel estimation coefficients, and the base station performs data transmission with the user device according to the precoding matrix.

Abstract: A gardening tool with identification function including an operating unit and a working unit is provided. The operating unit includes a first main body, a first electrical connector, and an operating device. The first electrical connector is set at one end of the first main body. The operating device includes a processor electrically connected to the first electrical connector. The processor stores operating parameters. The working unit includes a second main body, a second electrical connector, a motor, and a work piece. The electrical property of the second electrical connector is corresponding to one operating parameter in the processor. When the second main body is connected to the first main body, the second electrical connector is electrically connected to the first electrical connector. The processor selects one operating parameter according to the electrical property of the second electrical connector to control the output rotational speed or power of the motor.

Abstract: A method of manufacturing a semiconductor device that includes identifying a first area in the layout diagram which is populated with cells, the first area including first and second rows extending substantially parallel to a first direction, the first and second rows having substantially different cell densities; relative to a second direction, substantially perpendicular to the first direction, the first and second rows having corresponding first (H1) and second (H2) heights. The method also includes replacing cells in the first row which have the H1 height with corresponding substitute cells, each substitute cell being correspondingly taller relative to the second direction and correspondingly narrower relative to the first direction, the replacing thereby increasing a density of the second row at least without substantially increasing a density of the first row.

Abstract: A method of modifying an integrated circuit includes operations related to identifying at least two fin-containing functional areas of the integrated circuit, generating a performance curve for each fin-containing functional area of the integrated circuit for each fin height of a series of fin heights, and determining whether an inflection point exists for each performance curve. The method further includes operations related to selecting a value of a performance characteristic for each of the fin-containing functional areas, the selected value having a corresponding fin height in each of the fin-containing functional areas, modifying each fin-containing functional area to have the fin height corresponding to the selected value of the performance characteristic; and combining the modified fin-containing functional areas to form a modified integrated circuit.

Abstract: An ESD circuit is connected to a power pad and a first node. The ESD circuit includes a RC circuit and a first ESD current path. The RC circuit is connected between the power pad and the first node. The RC circuit is capable of providing a first control voltage and a second control voltage. The first ESD current path is connected between the power pad and the first node. When the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage and the second control voltages provided by the RC circuit, so that an ESD current flows from the power pad to the first node through the first ESD current path.

Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.

Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.

Abstract: The present disclosure provides a resource allocation method. The resource allocation method includes the following steps: selecting multiple first selected virtual nodes according to multiple virtual pheromonal trails on multiple virtual edges, in which the first selected virtual nodes forms at least one virtual tour, and the virtual tour includes multiple first virtual edges; updating the virtual pheromonal trails on the virtual edges according to virtual distances corresponding to the first virtual edges of the virtual tour; selecting multiple second selected virtual nodes according to the updated virtual pheromonal trails on the virtual edges, in which the second selected virtual nodes form at least one resulting virtual tour; allocating the resource blocks to selected user pairs according to the resulting virtual tour.

Abstract: A method and a system for encryption and decryption based on continuous-variable quantum neural network CVQNN. The method includes: updating a weight of the CVQNN with a training sample; triggering, by a sender, a legal measurement bases synchronization between the sender and the CVQNN; converting, by the sender, the information to be sent into a quadratic plaintext according to the synchronized measurement bases, and sending the quadratic plaintext to the CVQNN; encrypting, by the CVQNN, a received quadratic plaintext, and sending an encrypted quadratic plaintext to a receiver; after receiving the encrypted quadratic plaintext, sending by the receiver the encrypted quadratic plaintext to the CVQNN for decryption to obtain decrypted information. The embodiments implement data encryption and decryption by introducing CVQNN model and synchronization measurement technology. The embodiments provide advantages of high reliability, high security and easy realization.

Abstract: A method of generating a layout diagram includes: identifying a first area in the layout diagram which is populated with cells, the first area including first and second rows extending substantially parallel to a first direction, the first and second rows having substantially different cell densities; relative to a second direction, substantially perpendicular to the first direction, the first and second rows having corresponding first (H1) and second (H2) heights; for a first one of the cells having H1 height (a first H1 cell) in a first location in the first row, substituting a multi-row-height cell for the first H1 cell, the multi-row-height cell being narrower than the first H1 cell relative to the first direction; and placing a first part of the multi-row-height cell into a portion of the first location resulting in the first and second rows having more similar cell densities.