Abstract: A liquid crystal display panel is provided. The liquid crystal display panel includes: a first substrate and a second substrate arranged opposite to each other, and a liquid crystal layer and a plurality of strip-shaped spacers disposed between the first substrate and the second substrate. In the liquid crystal display panel, there is an overlapping area between an orthographic projection of a first signal line on a target base and an orthographic projection of a second signal line on the target base, and an orthographic projection of the strip-shaped spacer on the target base is not overlapped with the overlapping area.

Abstract: Methods and apparatus for processing a substrate are provided. In some embodiments, a method includes: depositing a metal buffer layer on a substrate and within a feature disposed in a dielectric layer of the substrate. The buffer layer is deposited using a first physical vapor deposition (PVD) process at a chamber pressure of less than 500 mTorr while applying less than or equal to 0.08 watts/cm2 of RF bias power to the substrate if the chamber pressure is less than or equal to 3 mTorr and applying less than or equal to 0.8 watts/cm2 of RF bias power to the substrate if the chamber pressure is greater than 3 mTorr. A metal liner layer is deposited atop the buffer layer using a second PVD process at a chamber pressure of less than or equal to 3 mTorr while applying greater than 0.08 watts/cm2 of RF bias power to the substrate.

Abstract: The present application provides a method for monitoring a gate oxide thickness: providing a device structure comprising a gate structure, a gate oxide layer under the gate structure, source and drain regions and a base region; applying a voltage ?Vdd on the gate structure so that an accumulation layer is formed between the source and drain regions, applying a small AC voltage on the basis of the gate voltage ?Vdd; grounding the source and drain regions; applying a voltage signal close to 0 potential on the base region; obtaining the capacitance Cox between the gate structure and the base region by testing; and obtaining the thickness of a gate oxide layer according to the formula Tox=?*S/Cox. This technique accurately monitors the thickness of the gate oxide layer, and avoids those errors caused by existing methods.

Abstract: An image management method includes: after a video stream sent by a camera is obtained, recognizing a face image in the video stream through face recognition; comparing the image with a face image that is in an area in which the camera is located in a database; and if the comparison fails, expanding the area in which the camera is located around, and then comparing the face image with face images in an area obtained after the area in which the camera is located is expanded.

Abstract: A charging station monitoring system including: a sensing device, a digital camera and a communication device which are arranged at a charging apparatus of a charging station, the sensing device and the digital camera each having a sensing range covering a parking lot associated with the charging apparatus and an area around the parking lot; a controller configured to determine an occupation state of the parking lot and/or detect and record an action of a third party or foreign object based on sensed information from the sensing device and the digital camera; and a charging assistance device configured to recommend an environmentally friendly charging station if an energy storage device of the electric vehicle has not been fully charged and needs to be further charged.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may identify that an uplink control information (UCI) payload satisfies a threshold size condition. The UE may map the UCI payload to an uplink control sequence. The UE may transmit a physical uplink control channel (PUCCH) that include the uplink control sequence to a base station. The uplink control sequence may be representative of the UCI payload. The base station may receive the PUCCH that includes the uplink control sequence from the UE. The base station may also determine the UCI payload by associating the uplink control sequence with a corresponding sequence index of the one or more sets of uplink control sequences.

Abstract: The present disclosure provides a direct current (DC) transformer error detection apparatus for a pulsating harmonic signal, including a DC and pulsating harmonic current output module and an external detected input module, where the DC and pulsating harmonic current output module outputs a DC and a DC superimposed pulsating harmonic current to an internal sampling circuit and a self-calibrated standard resistor array; and the internal sampling circuit converts the input DC and the input DC superimposed pulsating harmonic current into a voltage signal, and sends the voltage signal to an analog-to-digital (AD) sampling and measurement component through a front-end conditioning circuit and a detected input channel. The DC transformer error detection apparatus can complete self-calibration for measurement of the DC and the pulsating harmonic signal on a test site.

Abstract: Methods for reducing resistivity of metal gapfill include depositing a conformal layer in an opening of a feature and on a field of a substrate with a first thickness of the conformal layer of approximately 10 microns or less, depositing a non-conformal metal layer directly on the conformal layer at a bottom of the opening and directly on the field using an anisotropic deposition process. A second thickness of the non-conformal metal layer on the field and on the bottom of the feature is approximately 30 microns or greater. And depositing a metal gapfill material in the opening of the feature and on the field where the metal gapfill material completely fills the opening without any voids.

Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.

Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.

Abstract: A method of forming a semiconductor device structure includes forming a nucleation layer within at least one feature. The method includes exposing the nucleation layer to a nitrogen plasma treatment. The nitrogen plasma treatment preferentially treats the top field and sidewalls while leaving the bottom surface substantially untreated to encourage bottom up metal growth.

Abstract: A method and apparatus for tungsten gap-fill in semiconductor devices are provided. The method includes performing a gradient oxidation process to oxidize exposed portions of a liner layer, wherein the gradient oxidation process preferentially oxidizes an overhang portion of the liner layer, which obstructs or blocks top openings of one or more features formed within a field region of a substrate. The method further includes performing an etchback process to remove or reduce the oxidized overhang portion of the liner layer, exposing the liner layer to a chemical vapor transport (CVT) process to remove metal oxide remaining from the gradient oxidation process and the etchback process, and performing a tungsten gap-fill process to fill or partially fill the one or more features.

Abstract: A method for protecting a motor from overheating, includes: running a motor in a given parameter P and detecting a real-time temperature R of the motor; comparing the real-time temperature R with a plurality of set temperatures, the plurality of set temperatures including an overheating protection temperature Rm, shutdown temperature Rmax and recovery operation temperature Rmin, Rmin<Rm<Rmax; according to a comparison result, controlling the motor to operate at an initial current value I0, or operate in a reduced current value with respect to the initial current value I0, or stop running; and when the real-time temperature R meets the condition: Rm<R<Rmax, running the motor in an overheating protection mode, where the motor operates in a current value I lower than the initial current value I0, and the current value I decreases with the increase of the real-time temperature R.

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed in a first process chamber to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process is performed in the first process chamber removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

Abstract: Embodiments of methods and associated apparatus for filling a feature in a substrate are provided herein. In some embodiments, a method of depositing tungsten in features of a substrate includes: depositing a seed layer consisting essentially of tungsten in the features via a physical vapor deposition (PVD) process; and depositing a bulk layer consisting essentially of tungsten in the features via a chemical vapor deposition (CVD) process to fill the features such that the deposition of the bulk layer is selective to within the features as compared to a field region of the substrate, wherein the CVD process is performed by flowing hydrogen gas (H2) at a first flow rate and a tungsten precursor at a second flow rate, and wherein the first flow rate is less than the second flow rate.

Abstract: The present disclosure relates to a kit for detecting dust mite component-specific antibodies, and belongs to the technical field of antibody detection kits. The kit comprises a biotin-polystreptavidin-biotin-dust mite antigen-coated nitrocellulose (NC) membrane, a washing solution, an alkaline phosphatase (ALP)-labeled secondary antibody solution for dust mite component-specific antibodies, and a substrate solution. The kit may be used in cooperation with a fully automated instrument.

Abstract: A wellbore staged operation method, includes running, after a first well drifting operation is performed on a wellbore, a pipe string (100) in the wellbore, wherein the pipe string (100) includes, along a direction from bottom to top, a floating hoop (2), a plug seat (7), a toe-end sliding sleeve (3), and a fracturing sliding sleeve (4); performing a cementing operation, wherein cement slurry pumped into an inner chamber of the pipe string (100) enters an annulus between the pipe string and the wellbore through the plug seat (7) and the floating hoop (2) to form a cement sheath, the cement sheath isolating the toe-end sliding sleeve (3) from the fracturing sliding sleeve (4); performing a second drifting operation to ensure the toe-end sliding sleeve (3) of the pipe string (100) exposed; performing a pressure test for the pipe string; and performing staged fracturing constructions.

Abstract: This disclosure provides a test kit for testing a device under test (DUT) including a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having a nest and an interposer substrate installed under the nest.