Abstract: A semiconductor structure includes a substrate and a capacitor over the substrate. The capacitor includes a silicide layer over the substrate. The capacitor includes a first dielectric layer over the silicide layer. The capacitor includes a metal gate structure over the first dielectric layer, where a top portion of the metal gate structure is over the substrate and a bottom portion of the metal gate structure extends into the substrate. The capacitor includes a second dielectric layer over the metal gate structure. The capacitor further includes a conductive structure over the second dielectric layer.

Abstract: Methods of processing a substrate in a PVD chamber are provided herein. In some embodiments, a method of processing a substrate in a PVD chamber, includes: sputtering material from a target disposed in the PVD chamber and onto a substrate, wherein at least some of the material sputtered from the target is guided to the substrate through a magnetic field provided by one or more upper magnets disposed about a processing volume of the PVD chamber above a support pedestal for the substrate in the PVD chamber, one or more first magnets disposed about the support pedestal and providing an increased magnetic field strength at an edge region of the substrate, and one or more second magnets disposed below the support pedestal that increase a magnetic field strength at a central region of the substrate.

Abstract: Apparatus and methods of Hybrid Automatic Repeat Request (HARQ) Acknowledgement (ACK) feedback for multiple Physical Downlink Control Channel (PDCCH) based multiple Transmit Receive Points (TRP) transmission are disclosed. The apparatus includes: a receiver that receives a plurality of configurations of control resource sets (CORESETs), wherein each CORESET comprises a plurality of resource blocks (RBs) in frequency domain and a plurality of symbols in time domain, and time-frequency resources identified by the CORESET are used to transmit a Downlink Control Information (DCI); a processor that determines a Hybrid Automatic Repeat Request (HARQ) Acknowledgement (ACK) feedback selected from a group consisting of: a separate HARQ-ACK feedback and a joint HARQ-ACK feedback; and a transmitter that transmits the determined HARQ-ACK feedback; wherein the separate HARQ-ACK feedback is transmitted through a plurality of uplink resources; and the joint HARQ-ACK feedback is transmitted through one uplink resource.

Abstract: The present disclosure provides compounds that can inhibit the type III secretion system (TTSS) to decrease the pathogenesis of gram-negative bacteria. These compounds may have wide applications for treating bacteria diseases caused by gram-negative bacteria in a host species, including but not limited to, plants and animals. The present invention further relates to compositions that inhibit pathogenesis of gram-negative bacteria without killing the bacteria. Methods relating to preventing and/or treating infection of a host species by bacterial pathogens are also provided herein.

Abstract: Apparatus and methods to provide electronic devices comprising tungsten film stacks are provided. A tungsten liner formed by physical vapor deposition is filled with a tungsten film formed by chemical vapor deposition directly over the tungsten liner.

Abstract: Embodiments herein relate to a method, semiconductor device structures, and multi-chamber processing system for exposing a semiconductor device structure to an oxidizing plasma to form an oxide layer on at least one electrical connection formed in at least one feature formed within a dielectric layer of the semiconductor device structure, performing an etch process to remove the oxide layer and form an etch recess between a portion of the electrical connection and the dielectric layer At least a portion of the etch recess extends underneath at least a portion of the dielectric layer, and filling the at least one feature and the etch recess with a metal material.

Abstract: A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl5, MoCl6) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.

Abstract: A method of metal gapfill including depositing a metal layer on a dielectric layer present on a field and/or in an opening of a feature via plasma enhanced atomic layer deposition utilizing a metal halide precursor and a plasma comprising hydrogen and a noble gas; and depositing a metal gapfill material on the field and in the opening directly over the metal layer, wherein the metal gapfill material completely fills the opening.

Abstract: Embodiments of the disclosure include an apparatus and method of forming a semiconductor structure that includes metal contacts with a low resistance. In some embodiments, the semiconductor device generally includes an interconnect. The interconnect generally includes a dielectric layer with a tungsten (W) plug formed therein, a feature formed in the dielectric layer and over the W plug, a liner layer formed on an exposed surface of the W plug and on sidewalls of the feature, an interruption layer formed on the liner layer, and a conductive material substantially filling the feature. The liner layer includes molybdenum (Mo) or W, and the interruption layer includes Mo.

Abstract: Semiconductor devices and methods for molybdenum fill in semiconductor devices are provided. In one aspect, a method for processing a semiconductor device substrate is provided. The method includes exposing at least one feature formed in a dielectric layer to a grain modification layer deposition process to deposit a grain modification layer over at least a portion of the at least one feature. The at least one feature is defined by sidewall surfaces formed in the dielectric layer and a bottom surface extending between the sidewall surfaces. The method further includes exposing the at least one feature to a molybdenum deposition process to form a molybdenum-fill layer on the grain modification layer, wherein the grain modification layer comprises a metal different from molybdenum.

Abstract: Magnet assemblies comprising a housing with a top plate each comprising aligned openings are described. The housing has a bottom ring and an annular wall with a plurality of openings formed in the bottom ring. The top plate is on the housing and has a plurality of openings aligned with the plurality of openings in the bottom ring of the housing. The magnet assembly may also include a non-conducting base plate and/or a conductive cover plate. Methods for using the magnet assembly and magnetic field tuning are also described.

Abstract: An air blower, including a volute, a centrifugal wind wheel, and a motor. The volute includes an end plate, a side plate extending from an edge of the end plate, and a cavity formed by the end plate and the side plate; the centrifugal wind wheel is disposed in the cavity; the end plate includes an air inlet, and two ends of the side plate are disposed side by side to form an air outlet; the end plate further includes a support beam opposite to the air inlet, and the motor is disposed on the support beam.

Abstract: A differential-pressure sliding sleeve has an outer cylinder with a flow guiding hole being provided in a wall of the outer cylinder, an inner cylinder arranged in an inner cavity of the outer cylinder, an upper joint extending into the outer cylinder and fixedly connected to an upper end of the outer cylinder, a lower joint extending into the outer cylinder and fixedly connected to a lower end of the outer cylinder, and a dissolvable carrier ring arranged between the lower joint and the inner cylinder. An area of the axial upper end surface of the inner cylinder is greater than that of an axial lower end surface thereof, so that the working fluid generates a pressure difference to provide downward pressure for the inner cylinder, which moves downward under the pressure after the carrier ring is dissolved to open the flow guiding hole.

Abstract: Methods and apparatus for processing a substrate are provided. In some embodiments, a method includes depositing an amorphous interlayer atop a first layer on a substrate, wherein the first layer is a metal-containing layer, and depositing a metal layer atop the amorphous interlayer.

Abstract: A ? ray detector structure based on a p-i-n junction of perovskite and a calibration method are provided. An ultrathick intrinsic perovskite crystal grows by utilizing temperature inversion solution crystallization as a ? ray photon absorber, a p-type perovskite epitaxial layer grows on one side of the intrinsic perovskite crystal by adopting an epitaxial doping growing method, a n-type perovskite epitaxial layer grows on the other side, a dark state current and noise are inhibited by utilizing the p-i-n junction of perovskite, and a large-sized perovskite crystal is used to absorb and convert more ? photons. Detected signals at a cathode terminal and an anode terminal are measured simultaneously. The longitudinal interaction depths of the ? photons are calibrated according to the ratio of the two signals, and then detection events at the same depth are classified and counted respectively.

Abstract: Methods and apparatus for processing a substrate are provided. In some embodiments, a method includes: depositing a metal buffer layer on a substrate and within a feature disposed in a dielectric layer of the substrate. The buffer layer is deposited using a first physical vapor deposition (PVD) process at a chamber pressure of less than 500 mTorr while applying less than or equal to 0.08 watts/cm2 of RF bias power to the substrate if the chamber pressure is less than or equal to 3 mTorr and applying less than or equal to 0.8 watts/cm2 of RF bias power to the substrate if the chamber pressure is greater than 3 mTorr. A metal liner layer is deposited atop the buffer layer using a second PVD process at a chamber pressure of less than or equal to 3 mTorr while applying greater than 0.08 watts/cm2 of RF bias power to the substrate.

Abstract: Methods for reducing resistivity of metal gapfill include depositing a conformal layer in an opening of a feature and on a field of a substrate with a first thickness of the conformal layer of approximately 10 microns or less, depositing a non-conformal metal layer directly on the conformal layer at a bottom of the opening and directly on the field using an anisotropic deposition process. A second thickness of the non-conformal metal layer on the field and on the bottom of the feature is approximately 30 microns or greater. And depositing a metal gapfill material in the opening of the feature and on the field where the metal gapfill material completely fills the opening without any voids.

Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.

Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.

Abstract: A method of forming a semiconductor device structure includes forming a nucleation layer within at least one feature. The method includes exposing the nucleation layer to a nitrogen plasma treatment. The nitrogen plasma treatment preferentially treats the top field and sidewalls while leaving the bottom surface substantially untreated to encourage bottom up metal growth.