Patents by Inventor Wei Lei
Wei Lei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250109148Abstract: It relates generally to GLP-1 agonists and pharmaceutical compositions comprising the same, as well as methods for treating a GLP-1 associated disease, disorder, or condition.Type: ApplicationFiled: January 20, 2023Publication date: April 3, 2025Inventors: Wei HUANG, Hui LEI, Qinghua MENG, Fan WU, Weiqiang XING, Haizhen ZHANG
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Publication number: 20250105983Abstract: Apparatus and methods of Hybrid Automatic Repeat Request (HARQ) Acknowledgement (ACK) feedback for multiple Physical Downlink Control Channel (PDCCH) based multiple Transmit Receive Points (TRP) transmission are disclosed. The apparatus includes: a receiver that receives a plurality of configurations of control resource sets (CORESETs), wherein each CORESET comprises a plurality of resource blocks (RBs) in frequency domain and a plurality of symbols in time domain, and time-frequency resources identified by the CORESET are used to transmit a Downlink Control Information (DCI); a processor that determines a Hybrid Automatic Repeat Request (HARQ) Acknowledgement (ACK) feedback selected from a group consisting of: a separate HARQ-ACK feedback and a joint HARQ-ACK feedback; and a transmitter that transmits the determined HARQ-ACK feedback; wherein the separate HARQ-ACK feedback is transmitted through a plurality of uplink resources; and the joint HARQ-ACK feedback is transmitted through one uplink resource.Type: ApplicationFiled: December 10, 2024Publication date: March 27, 2025Applicant: Lenovo (Beijing) LimitedInventors: Bingchao Liu, Chenxi Zhu, Haipeng Lei, Wei Ling
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Publication number: 20250095116Abstract: An improved systems and methods for generating a denoised inspection image are disclosed. An improved method for generating a denoised inspection image comprises acquiring an inspection image; generating a first denoised image by executing a first type denoising algorithm on the inspection image; and generating a second denoised image by executing a second type denoising algorithm on the first denoised image.Type: ApplicationFiled: April 28, 2022Publication date: March 20, 2025Applicant: ASML Netherlands B.V.Inventors: Hairong LEI, Wei FANG
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Publication number: 20250079199Abstract: A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.Type: ApplicationFiled: August 29, 2023Publication date: March 6, 2025Inventors: Shiyu YUE, Sahil Jaykumar PATEL, Yu LEI, Wei LEI, Chih-Hsun HSU, Yi XU, Abulaiti HAIRISHA, Cong TRINH, Yixiong YANG, Ju Hyun OH, Aixi ZHANG, Xingyao GAO, Rongjun WANG
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Patent number: 12237794Abstract: A method for protecting a motor from overheating, includes: running a motor in a given parameter P and detecting a real-time temperature R of the motor; comparing the real-time temperature R with a plurality of set temperatures, the plurality of set temperatures including an overheating protection temperature Rm, shutdown temperature Rmax and recovery operation temperature Rmin, Rmin<Rm<Rmax; according to a comparison result, controlling the motor to operate at an initial current value I0, or operate in a reduced current value with respect to the initial current value I0, or stop running; and when the real-time temperature R meets the condition: Rm<R<Rmax, running the motor in an overheating protection mode, where the motor operates in a current value I lower than the initial current value I0, and the current value I decreases with the increase of the real-time temperature R.Type: GrantFiled: January 13, 2023Date of Patent: February 25, 2025Assignee: ZHONGSHAN BROAD-OCEAN MOTOR CO., LTD.Inventors: Xiaosan Xu, Hairong Sun, Wei Lei, Jie Zhang
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Patent number: 12232493Abstract: The present disclosure is related to terrein functioning as a biopesticide formulation in drought resistance and growth promotion of crops. The formulation containing terrein can be treated by soaking or spraying on the crops. It is especially suitable for drought and water shortage conditions, promoting growth of plant root length, seedling height, fresh weight, and dry weight, greatly increasing crop yield, and significantly improving drought resistance of crop plants. Under the condition of seed soaking treatment with 10 ?g/mL terrein, promotion rates of root length, seedling height, fresh weight, and dry weight of pakchoi are 99.19%, 15.66%, 40.34%, and 49.12%, respectively. The source of terrein is easy to obtain and the cost is low. It has a simple structure and is easily soluble in water. In the actual application process, it only needs to simply prepare an aqueous solution or mix with other pesticide formulations for seed soaking or spraying treatment.Type: GrantFiled: July 7, 2023Date of Patent: February 25, 2025Assignee: XINJIANG INSTITUTE OF ECOLOGY AND GEOGRAPHY, CHINESE ACADEMY OF SCIENCESInventors: Hua Shao, Lijing Lei, Wei Shao, Chi Zhang
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Publication number: 20250056819Abstract: A capacitor structure and methods of forming the same are described. In some embodiments, the structure includes a first well region, a first semiconductor layer disposed over the first well region, a second semiconductor layer disposed on the first semiconductor layer, and a dielectric layer disposed on the second semiconductor layer. The dielectric layer has a top surface, a bottom surface, one or more protrusions extending towards the second semiconductor layer, and one or more openings in the top surface. The structure further includes a gate structure disposed on the dielectric layer.Type: ApplicationFiled: January 2, 2024Publication date: February 13, 2025Inventors: Wei-Lun Chung, Chung-Lei Chen, Anhao Cheng, Chien-Wei Lee, Yen-Liang Lin, Ru-Shang Hsiao
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Differential pressure sliding sleeve, and oil and gas well fracturing construction method using same
Patent number: 12215580Abstract: A differential-pressure sliding sleeve has an outer cylinder with a flow guiding hole being provided in a wall of the outer cylinder, an inner cylinder arranged in an inner cavity of the outer cylinder, an upper joint extending into the outer cylinder and fixedly connected to an upper end of the outer cylinder, a lower joint extending into the outer cylinder and fixedly connected to a lower end of the outer cylinder, and a dissolvable carrier ring arranged between the lower joint and the inner cylinder. An area of the axial upper end surface of the inner cylinder is greater than that of an axial lower end surface thereof, so that the working fluid generates a pressure difference to provide downward pressure for the inner cylinder, which moves downward under the pressure after the carrier ring is dissolved to open the flow guiding hole.Type: GrantFiled: June 10, 2021Date of Patent: February 4, 2025Assignees: CHINA PETROLEUM & CHEMICAL CORPORATION, SINOPEC SOUTHWEST OIL & GAS COMPANYInventors: Shunqu Hu, Yongmao Lin, Wei Zhao, Wei Lei, Zhi Xie, Zhimin Hou, Chen Chen, Qiang Wang, Dan Hu, Jingyu Cui -
Publication number: 20250040157Abstract: A semiconductor structure includes a substrate and a capacitor over the substrate. The capacitor includes a silicide layer over the substrate. The capacitor includes a first dielectric layer over the silicide layer. The capacitor includes a metal gate structure over the first dielectric layer, where a top portion of the metal gate structure is over the substrate and a bottom portion of the metal gate structure extends into the substrate. The capacitor includes a second dielectric layer over the metal gate structure. The capacitor further includes a conductive structure over the second dielectric layer.Type: ApplicationFiled: October 26, 2023Publication date: January 30, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Liang Hsu, Chung-Lei Chen, Anhao Cheng, Yen-Liang Lin, Ru-Shang Hsiao
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Patent number: 12203163Abstract: Methods of processing a substrate in a PVD chamber are provided herein. In some embodiments, a method of processing a substrate in a PVD chamber, includes: sputtering material from a target disposed in the PVD chamber and onto a substrate, wherein at least some of the material sputtered from the target is guided to the substrate through a magnetic field provided by one or more upper magnets disposed about a processing volume of the PVD chamber above a support pedestal for the substrate in the PVD chamber, one or more first magnets disposed about the support pedestal and providing an increased magnetic field strength at an edge region of the substrate, and one or more second magnets disposed below the support pedestal that increase a magnetic field strength at a central region of the substrate.Type: GrantFiled: May 28, 2021Date of Patent: January 21, 2025Assignee: APPLIED MATERIALS, INC.Inventors: Goichi Yoshidome, Suhas Bangalore Umesh, Sushil Arun Samant, Martin Lee Riker, Wei Lei, Kishor Kumar Kalathiparambil, Shirish A. Pethe, Fuhong Zhang, Prashanth Kothnur, Andrew Tomko
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Patent number: 12206622Abstract: Apparatus and methods of Hybrid Automatic Repeat Request (HARQ) Acknowledgement (ACK) feedback for multiple Physical Downlink Control Channel (PDCCH) based multiple Transmit Receive Points (TRP) transmission are disclosed. The apparatus includes: a receiver that receives a plurality of configurations of control resource sets (CORESETs), wherein each CORESET comprises a plurality of resource blocks (RBs) in frequency domain and a plurality of symbols in time domain, and time-frequency resources identified by the CORESET are used to transmit a Downlink Control Information (DCI); a processor that determines a Hybrid Automatic Repeat Request (HARQ) Acknowledgement (ACK) feedback selected from a group consisting of: a separate HARQ-ACK feedback and a joint HARQ-ACK feedback; and a transmitter that transmits the determined HARQ-ACK feedback; wherein the separate HARQ-ACK feedback is transmitted through a plurality of uplink resources; and the joint HARQ-ACK feedback is transmitted through one uplink resource.Type: GrantFiled: August 1, 2019Date of Patent: January 21, 2025Assignee: Lenovo (Beijing) LimitedInventors: Bingchao Liu, Chenxi Zhu, Haipeng Lei, Wei Ling
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Publication number: 20250019341Abstract: The present disclosure provides compounds that can inhibit the type III secretion system (TTSS) to decrease the pathogenesis of gram-negative bacteria. These compounds may have wide applications for treating bacteria diseases caused by gram-negative bacteria in a host species, including but not limited to, plants and animals. The present invention further relates to compositions that inhibit pathogenesis of gram-negative bacteria without killing the bacteria. Methods relating to preventing and/or treating infection of a host species by bacterial pathogens are also provided herein.Type: ApplicationFiled: June 6, 2024Publication date: January 16, 2025Inventors: Xiaoguang LEI, Jian-Min Zhou, Haijun Wang, Pei Miao, Wei Wang
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Patent number: 12191198Abstract: Apparatus and methods to provide electronic devices comprising tungsten film stacks are provided. A tungsten liner formed by physical vapor deposition is filled with a tungsten film formed by chemical vapor deposition directly over the tungsten liner.Type: GrantFiled: August 25, 2020Date of Patent: January 7, 2025Assignee: Applied Materials, Inc.Inventors: Feihu Wang, Joung Joo Lee, Xi Cen, Zhibo Yuan, Wei Lei, Kai Wu, Chunming Zhou, Zhebo Chen
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Publication number: 20250006518Abstract: Embodiments herein relate to a method, semiconductor device structures, and multi-chamber processing system for exposing a semiconductor device structure to an oxidizing plasma to form an oxide layer on at least one electrical connection formed in at least one feature formed within a dielectric layer of the semiconductor device structure, performing an etch process to remove the oxide layer and form an etch recess between a portion of the electrical connection and the dielectric layer At least a portion of the etch recess extends underneath at least a portion of the dielectric layer, and filling the at least one feature and the etch recess with a metal material.Type: ApplicationFiled: June 25, 2024Publication date: January 2, 2025Inventors: Shiyu YUE, Wei LEI, Yu LEI, Ju Hyun OH, Zhimin QI, Sahil Jaykumar PATEL, Yi XU, Aixi ZHANG, Bingqian LIU, Cong TRINH, Xianmin TANG, Hayrensa ABLAT
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Publication number: 20240420947Abstract: A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl5, MoCl6) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.Type: ApplicationFiled: June 16, 2023Publication date: December 19, 2024Inventors: Shiyu YUE, Jiajie CEN, Sahil Jaykumar PATEL, Zhimin QI, Ju Hyun OH, Aixi ZHANG, Xingyao GAO, Wei LEI, Yi XU, Yu LEI, Tsung-Han YANG, Xiaodong WANG, Xiangjin XIE, Yixiong YANG, Kevin KASHEFI, Rongjun WANG
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Publication number: 20240395614Abstract: A method of metal gapfill including depositing a metal layer on a dielectric layer present on a field and/or in an opening of a feature via plasma enhanced atomic layer deposition utilizing a metal halide precursor and a plasma comprising hydrogen and a noble gas; and depositing a metal gapfill material on the field and in the opening directly over the metal layer, wherein the metal gapfill material completely fills the opening.Type: ApplicationFiled: May 26, 2023Publication date: November 28, 2024Applicants: TOYOTA RESEARCH INSTITUTE, INC., TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yi XU, Yu LEI, Aixi ZHANG, Bingqian LIU, Zhimin QI, Wei LEI, Rongjun WANG
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Publication number: 20240371771Abstract: Embodiments of the disclosure include an apparatus and method of forming a semiconductor structure that includes metal contacts with a low resistance. In some embodiments, the semiconductor device generally includes an interconnect. The interconnect generally includes a dielectric layer with a tungsten (W) plug formed therein, a feature formed in the dielectric layer and over the W plug, a liner layer formed on an exposed surface of the W plug and on sidewalls of the feature, an interruption layer formed on the liner layer, and a conductive material substantially filling the feature. The liner layer includes molybdenum (Mo) or W, and the interruption layer includes Mo.Type: ApplicationFiled: January 26, 2024Publication date: November 7, 2024Inventors: Sahil Jaykumar PATEL, Wei LEI, Tuerxun AILIHUMAER, Joung Joo LEE, Rongjun WANG, Xianmin TANG
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Publication number: 20240355673Abstract: Semiconductor devices and methods for molybdenum fill in semiconductor devices are provided. In one aspect, a method for processing a semiconductor device substrate is provided. The method includes exposing at least one feature formed in a dielectric layer to a grain modification layer deposition process to deposit a grain modification layer over at least a portion of the at least one feature. The at least one feature is defined by sidewall surfaces formed in the dielectric layer and a bottom surface extending between the sidewall surfaces. The method further includes exposing the at least one feature to a molybdenum deposition process to form a molybdenum-fill layer on the grain modification layer, wherein the grain modification layer comprises a metal different from molybdenum.Type: ApplicationFiled: April 20, 2023Publication date: October 24, 2024Inventors: Wei LEI, Sahil PATEL, Yixiong YANG, Yu LEI, Shiyu YUE, Yi XU, Tuerxun AILIHUMAER, Juhyun OH, Xianmin TANG, Rongjun WANG
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Patent number: 12112890Abstract: Magnet assemblies comprising a housing with a top plate each comprising aligned openings are described. The housing has a bottom ring and an annular wall with a plurality of openings formed in the bottom ring. The top plate is on the housing and has a plurality of openings aligned with the plurality of openings in the bottom ring of the housing. The magnet assembly may also include a non-conducting base plate and/or a conductive cover plate. Methods for using the magnet assembly and magnetic field tuning are also described.Type: GrantFiled: September 17, 2021Date of Patent: October 8, 2024Assignee: Applied Materials, Inc.Inventors: Borui Xia, Anthony Chih-Tung Chan, Shiyu Yue, Wei Lei, Aravind Miyar Kamath, Mukund Sundararajan, Rongjun Wang, Adolph Miller Allen
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Patent number: D1068739Type: GrantFiled: November 30, 2023Date of Patent: April 1, 2025Assignee: Ningbo Sogen Electronics Technology Co., Ltd.Inventors: Hao Zhang, Ronghua Zhu, Wei Zhao, Diqiu Chen, Shundong Pan, Yuqing Lei, Tianshuo Zhang