Abstract: An illumination panel device includes a housing, a first circuit board, a second circuit board, and a light guide. The housing includes a frame coupled to a rear cover. The frame defines an opening. The first circuit board includes a plurality of white light emitters. The first circuit board is coupled to the frame such that the plurality of white light emitters are arranged around the opening. The second circuit board includes a plurality of multi-color light emitters. The second circuit board is coupled to the frame such that the plurality of multi-color light emitters are arranged around the opening. The light guide has opposite front and back surfaces. The light guide is arranged in the opening with the back surface facing the rear cover. The light guide is optically coupled to at least the plurality of white light emitters through peripheral edges of the light guide.

Abstract: Provided are methods of continuous counterflow centrifugation for the manufacturing of cell compositions, including for the production of T cell therapies including cells that express recombinant receptors such as chimeric antigen receptors (CARs).

Abstract: A lamp including a light emitting module having a base substrate with a mounting surface, a plurality of white-light emitting elements disposed on the mounting surface in a circular arrangement with a central axis extending from a center thereof, an elongated support structure extending longitudinally along the central axis from the mounting surface, and at least one row of red-green-blue-light emitting elements distributed along the elongated support structure lengthwise. The lamp further including a light diffuser cover placed over the plurality of white-light emitting elements with the elongated support structure inserted therethrough, and a hollow lamp shade fitted over the light emitting module to surround the elongated support structure with a base opening of the hollow lamp shade interfacing the base substrate, wherein a rim of the base opening encircle the plurality of white-light emitting elements capable of illuminating the hollow lamp shade from the base opening.

Abstract: A system can include a memory; and a processing device, operatively coupled with the memory, to perform operations including: partitioning the memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier; receiving a host command to access data; identifying a compression ratio of the data; identifying a memory partition among the plurality of memory partitions; identifying a location among a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a compression ratio range associated with the memory partition; and performing an operation regarding the data at the identified location on the memory partition.

Abstract: Embodiments of the disclosure include an apparatus and method of forming a backside profile in a semiconductor device that includes die-to-wafer bonding. The method generally includes removing a portion of a substrate layer included in a plurality of dies, the plurality of dies arranged on and bonded to an insulation layer included in a support structure, where the plurality of dies define a plurality of channels between adjacent dies, and forming a corner feature on a plurality of corners of the substrate layer adjacent to the plurality of channels. The use of a backside profile as described herein may mitigate the downstream process risks associated with trapped residue in the channels, and provide stress relief to the semiconductor device.

Abstract: A method for depositing copper onto a substrate includes grain engineering to control the internal structure of the copper. In some embodiments, the method comprises depositing a grain control layer conformally onto a copper seed layer in a structure on the substrate where the grain control layer is a non-conducting material, etching the grain control layer using a direct deep reactive ion etch (DRIE) process to remove portions of the grain control layer on horizontal surfaces within the structure, and depositing a copper material onto the structure such that at least one grain parameter of the copper material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the structure. In some embodiments, the deposited copper material in the structure has a <111> grain orientation normal to a horizontal surface of the structure.

Abstract: A lamp including a light emitting module having a base substrate with a mounting surface, a plurality of white-light emitting elements disposed on the mounting surface in a circular arrangement with a central axis extending from a center thereof, an elongated support structure extending longitudinally along the central axis from the mounting surface, and at least one row of red-green-blue-light emitting elements distributed along the elongated support structure lengthwise. The lamp further including a light diffuser cover placed over the plurality of white-light emitting elements with the elongated support structure inserted therethrough, and a hollow lamp shade fitted over the light emitting module to surround the elongated support structure with a base opening of the hollow lamp shade interfacing the base substrate, wherein a rim of the base opening encircle the plurality of white-light emitting elements capable of illuminating the hollow lamp shade from the base opening.

Abstract: Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.

Abstract: Methods, systems, and devices for interface techniques for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute memory access circuitry among multiple semiconductor dies of a stack. A first die of the system may include logic circuitry operable to configure a set of multiple first interface blocks of the first die. Each first interface block may include circuitry operable to communicate with one or more second interface blocks of one or more second dies of the system to access a respective set of one or more memory arrays of the one or more second dies. In some examples, the system may include a respective controller for each first interface block to support access operations via the first interface block. The system may also include non-volatile storage, one or more sensors, or a combination thereof to support various operations of the system.

Abstract: A method, system and computer program product for diagnosing a malfunctioning or misused electronic device is disclosed. The method includes performing analytics on at least one of video and audio to automatically detect at least one anomaly exhibited by the electronic device or exhibited in relation to user interaction with the electronic device, the at least one anomaly being distinguishable from other non-present anomalies detectable by a computer system that carries out the performing of the analytics.

Abstract: A transcorneal electrical stimulation (TES) apparatus for treating brain diseases is provided. The apparatus includes an eye-contacting interface with at least one active electrode, an inactive reference electrode, and a current source. Both the active and reference electrodes are electrically connected to the current source, facilitating transcorneal electrical stimulation for various applications.

Abstract: The present disclosure provides an apparatus and a method for determining a location-spoofing application, the method comprising: generating a numeric representation of an application name of an application used for generating a geolocation position signal of a user using a variable derived from a list of application names relating to a plurality of other applications capable of generating a geolocation position signal of a user; and determining a prediction on whether the application is a location-spoofing application based on a scale of the generated numeric representation of the application name.

Abstract: A method and apparatus for training a learning model for automatic defect detection and classification of at least a portion of a processed wafer include receiving labeled images having defect classification types and features for portions of a post-processed wafer, creating a first training set comprising the received labeled images, training the machine learning model to automatically classify wafer portions based on at least one detected defect in respective wafer portions using the first training set, receiving labeled wafer profiles having respective downstream yield data, creating a second training set comprising the labeled wafer profiles and training the machine learning model, using the second training set, to automatically determine a respective downstream yield of a wafer based on a respective wafer profile. The machine learning model can be applied to at least one unlabeled wafer image to determine at least one defect classification for at least one portion of a wafer.

Abstract: A method, apparatus and system for the automatic detection and measurement of chipping defects on diced wafers includes receiving an image of at least a portion of a diced wafer, aligning the received image of the at least the portion of the diced wafer, determining edges of the at least the portion of the diced wafer depicted in the aligned, received image, automatically determining at least one baseline from which to measure chipping defects on the at least the portion of the diced wafer from the determined edges, and measuring chipping defects on the at least the portion of the diced wafer using at least one determined, respective baseline. In some embodiments, the method, apparatus and system can further include applying a machine learning model to measured chipping defects to determine if a critical failure exists on the diced wafer.

Abstract: A lamp including a light emitting module having a base substrate with a mounting surface, a plurality of white-light emitting elements disposed on the mounting surface in a circular arrangement with a central axis extending from a center thereof, an elongated support structure extending longitudinally along the central axis from the mounting surface, and at least one row of red-green-blue-light emitting elements distributed along the elongated support structure lengthwise. The lamp further including a light diffuser cover placed over the plurality of white-light emitting elements with the elongated support structure inserted therethrough, and a hollow lamp shade fitted over the light emitting module to surround the elongated support structure with a base opening of the hollow lamp shade interfacing the base substrate, wherein a rim of the base opening encircle the plurality of white-light emitting elements capable of illuminating the hollow lamp shade from the base opening.

Abstract: A method and apparatus for training a learning model for the automatic detection and classification of defects on wafers includes receiving labeled images of wafer defects having multiple defect classifications, creating a first training set including the received labeled images of wafer defects, training the machine learning model to automatically detect and classify wafer defects in a first stage using the first training set, blending at least one set of at least two labeled images having different classifications to generate additional labeled image data, creating a second training set including the blended, additional labeled image data, and training the machine learning model to automatically detect and classify wafer defects in a second stage using the second training set. The trained machine learning model can then be applied to at least one unlabeled wafer image to determine at least one defect classification for the at least one unlabeled wafer image.

Abstract: Described herein is a composition for delivery of an active agent. The composition includes a peptide coacervate, wherein the peptide coacervate includes one or more peptides derived from histidine-rich proteins, and an active agent encapsulated in the peptide coacervate. Further provided are a method for encapsulation of an active agent in a peptide coacervate, a method for delivery of an active agent, and a method for treating or diagnosing a condition or disease in a subject in need thereof.

Abstract: The invention relates to a method to determine authenticity of a security feature of an identification document, comprising: receiving a real-time video feed of the identification document with a light source directed at the identification document to make visible a security hologram; processing the real-time video feed into a plurality of image sequence; analysing each image from the plurality of image sequence for a glare and the security hologram, wherein the glare is a reflection of the light source from the identification document; analysing the position of the glare and the security hologram in each image; evaluating whether the position of the glare and the position of the security hologram is caused by the light source; providing authenticity result of the identification document captured from the real-time video feed, and using an algorithm to generate a random designated region for the light source to be positioned to.

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

Abstract: An illumination panel device includes a housing, a first circuit board, a second circuit board, and a light guide. The housing includes a frame coupled to a rear cover. The frame defines an opening. The first circuit board includes a plurality of white light emitters. The first circuit board is coupled to the frame such that the plurality of white light emitters are arranged around the opening. The second circuit board includes a plurality of multi-color light emitters. The second circuit board is coupled to the frame such that the plurality of multi-color light emitters are arranged around the opening. The light guide has opposite front and back surfaces. The light guide is arranged in the opening with the back surface facing the rear cover. The light guide is optically coupled to at least the plurality of white light emitters through peripheral edges of the light guide.